AK4342 Datasheet, PDF (17/43 Pages) Asahi Kasei Microsystems – 24-Bit Stereo DAC with HP-AMP & 2V Line-Out

ASAHI KASEI
[AK4342]
„ Serial Data Interface
The AK4342 interfaces with external system via the SDATA, BICK and LRCK pins. Five data formats are supported and
are selected by the DIF2, DIF1 and DIF0 bits (Table 4). Mode 0 is compatible with existing 16bit DACs and digital filters.
Mode 1 is a 20bit version of Mode 0. Mode 4 is a 24bit version of Mode 0. Mode 2 is similar to AKM ADCs and many
DSP serial ports. Mode 3 is compatible with the I²S serial data protocol. In Modes 2 and 3 with BICK≥48fs, the following
formats are also valid: 16-bit data followed by eight zeros (17th to 24th bits) and 20-bit data followed by four zeros (21st
to 24th bits). In all modes, the serial data is MSB first and 2’s complement format. The polarity of BICK can be inverted
by the BCKP bit, the polarity of LRCK can be inverted by the LRP bit. PMDAC bit should be set to “0” when BCKP or
LRP bits are changed.
DIF2
bit
0
0
0
0
1
DIF1
bit
0
0
1
1
0
DIF0
bit
0
1
0
1
0
MODE
BICK
0: 16bit, LSB justified
32fs ≤ BICK ≤ 128fs (Half/Normal Speed Mode)
32fs ≤ BICK ≤ 64fs (Double Speed Mode)
1: 20bit, LSB justified
40fs ≤ BICK ≤ 128fs (Half/Normal Speed Mode)
40fs ≤ BICK ≤ 64fs (Double Speed Mode)
2: 24bit, MSB justified
48fs ≤ BICK ≤ 128fs
48fs ≤ BICK ≤ 64fs
(Half/Normal Speed Mode)
(Double Speed Mode)
BICK=32fs (Half/Normal/Double Speed Mode)
3: I²S Compatible
or
48fs ≤ BICK ≤ 128fs (Half/Normal Speed Mode)
48fs ≤ BICK ≤ 64fs (Double Speed Mode)
4: 24bit, LSB justified
48fs ≤ BICK ≤ 128fs (Half/Normal Speed Mode)
48fs ≤ BICK ≤ 64fs (Double Speed Mode)
Table 4. Audio Data Format
Figure
Figure 12
Figure 13
Figure 14 Default
Figure 15
Figure 13
BCPKP bit
0
0
1
1
LRP bit
0
1
0
1
LRCK Polarity
BICK Polarity
Lch Data
Rch Data
(SDATA Latch Timing)
H: Mode 0,1,2,4
L: Mode 3
L: Mode 0,1,2,4
H: Mode 3
↑
L: Mode 0,1,2,4
H: Mode 3
H: Mode 0,1,2,4
L: Mode 3
↑
H: Mode 0,1,2,4
L: Mode 3
L: Mode 0,1,2,4
H: Mode 3
↓
L: Mode 0,1,2,4
H: Mode 3
H: Mode 0,1,2,4
L: Mode 3
↓
Table 5. LRCK and BICK Polarities
Default
LRCK
BICK
(32fs)
SDATA
Mode 0
BICK
15 14
6 5 4 3 2 1 0 15 14
6 5 4 3 2 1 0 15 14
SDATA
Mode 0
Don’t care
15:MSB, 0:LSB
15 14
0 Don’t care
15 14
0
Lch Data
Rch Data
Figure 12. Mode 0 Timing (BCKP bit = “0”, LRP bit = “0”)
MS0506-E-02
- 17 -
2006/07