AK4342 Datasheet, PDF (27/43 Pages) Asahi Kasei Microsystems – 24-Bit Stereo DAC with HP-AMP & 2V Line-Out

ASAHI KASEI
[AK4342]
„ System Reset
PDN pin must keep “L” until all power supply pins (AVDD, DVDD, PVDD, HVDD and TVDD) are applied. After they
are applied, PDN pin must be set to “H”. After exiting reset (PDN pin: “L” Æ “H”), all blocks (VCOM, DAC, HPL, HPR,
LAUX, RAUX, LOUT, ROUT and charge pump circuit) switch to the power-down state. The contents of the control
register are maintained until the reset is done.
DAC exits reset and power down state by MCLK edge after PMDAC bit is changed to “1”, and then DAC is powered up
and the internal timing starts clocking by LRCK edge. DAC is in power-down mode until MCLK and LRCK are input.
„ Power-Up/Down Sequence
Power Supply
PDN pin
PMVCM bit
Clock Input
(1)
(2) (4)
(3)
PMCP bit
Don’t care
Don’t care
PVEE pin
0V
PMDAC bit
PVEE
0V
(10)
DAC Internal
State
Power Down
Normal Operation
PMHP bit
(or PMLO bit)
(5)
HMUTEL/R bits
(or LMUTE bit)
HPL/HPR pins
(or LOUT/ROUT pins)
0V
MUTE
Normal MUTE
0V
PMLO bit
(or PMHP bit)
(6) (7)
(8) (9)
LMUTE bit
(or HMUTEL/R bit)
LOUT/ROUT pins
(or HPL/HPR pins)
0V
MUTE
Normal MUTE
(6) (7)
(8) (9)
Figure 20. Example of Power-up/down Sequence
Power Down
0V
(1) After Power Up: PDN pin “L” Æ “H”
“L” time (1) of 150ns or more is needed to reset the AK4342.
PDN pin must keep “L” until all power supply pins (AVDD, DVDD, PVDD, HVDD and TVDD) are applied.
After they are applied, PDN pin must be set to “H”.
(2) DFS1-0, DIF2-0, DEM1-0, FS3-0, PTS1-0, STS1-0, PUT1-0, LRP, BCKP and DACLR bits should be set during this
period before the DAC and charge pump circuit are powered-up.
(3) Supply the external clocks (MCLK, BICK, LRCK)
MS0506-E-02
- 27 -
2006/07