AK4342 Datasheet, PDF (16/43 Pages) Asahi Kasei Microsystems – 24-Bit Stereo DAC with HP-AMP & 2V Line-Out

ASAHI KASEI
[AK4342]
OPERATION OVERVIEW
„ System Clock
The external clocks required to operate the AK4342 are MCLK, BICK and LRCK. MCLK should be synchronized with
LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter, delta-sigma modulator,
charge pump circuit and counter for transition time. The MCLK frequency is detected from the relation between MCLK
and LRCK automatically. The Half speed, the Normal speed and the Double speed mode are selected with the DFS1-0
pins (Table 1). The sampling frequency is selected with the FS3-0 bits. (Table 2)
When the states of DFS1-0 bits change in the normal operation mode, the AK4342 should be reset by PDN pin or
PMDAC bit.
DFS1 bit
0
0
1
1
DFS0 bit
0
1
0
1
Mode
fs
MCLK Frequency
Normal Speed 8 ∼ 48kHz
256/384/512/768fs
Double Speed 60 ∼ 96kHz
128/192/256/384fs
Half Speed 8 ∼ 24kHz
512/768fs
Reserve
Table 1. System Clock Example
Default
FS3 bit
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FS2 bit
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS1 bit
FS0 bit
Sampling Frequency
0
0
44.1kHz
0
1
32kHz
1
0
48kHz
1
1
(Reserve)
0
0
88.2kHz
0
1
64kHz
1
0
96kHz
1
1
(Reserve)
0
0
22.05kHz
0
1
16kHz
1
0
24kHz
1
1
(Reserve)
0
0
11.025kHz
0
1
8kHz
1
0
12kHz
1
1
(Reserve)
Table 2. Set up of Sampling Frequency
Default
For low sampling rates, DR and S/N degrade because of the out-of-band noise. DR and S/N are improved by setting the
half speed mode (DFS1-0 bits = “10”)
Mode
S/N (fs=8kHz, 20kLPF + A-weighted)
Lineout
Headphone
Aux-out
Normal Speed
89dB
87dB
87dB
Half Speed
99dB
95dB
95dB
Table 3. Relationship between Clock Mode and S/N of Lineout, Headphone and Aux-out
External clocks (MCLK, BICK and LRCK) should always be present whenever the DAC, headphone amp, lineout amp or
charge pump circuits is in normal operation mode (PMDAC bit = “1”, PMHP bit = “1”, PMLO bit = “1” or PMCP bit =
“1”). If these clocks are not provided, the AK4342 is not operated normally, especially, DAC may draw excess current
due to dynamic refresh of internal logic. If the external clocks are not present, the DAC, headphone amp, charge pump
circuit and lineout amp should be in the power-down mode (PMDAC bit = PMHP bit = PMLO bit = PMCP bit = “0”).
MS0506-E-02
- 16 -
2006/07