AK4342 Datasheet, PDF (12/43 Pages) Asahi Kasei Microsystems – 24-Bit Stereo DAC with HP-AMP & 2V Line-Out

ASAHI KASEI
[AK4342]
SWITCHING CHARACTERISTICS (Continued)
(Ta=25°C; AVDD, DVDD, HVDD, PVDD=2.7 ∼ 3.6V; TVDD=2.7 ∼ 3.6V)
Parameter
Symbol
min
typ
Control Interface Timing (I²C Bus mode): (Note 29)
SCL Clock Frequency
fSCL
-
-
Bus Free Time Between Transmissions
tBUF
1.3
-
Start Condition Hold Time (prior to first clock pulse) tHD:STA
0.6
-
Clock Low Time
tLOW
1.3
-
Clock High Time
tHIGH
0.6
-
Setup Time for Repeated Start Condition
tSU:STA
0.6
-
SDA Hold Time from SCL Falling
(Note 30) tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT
0.1
-
Rise Time of Both SDA and SCL Lines
tR
-
-
Fall Time of Both SDA and SCL Lines
tF
-
-
Setup Time for Stop Condition
tSU:STO
0.6
-
Capacitive load on bus
Cb
-
Pulse Width of Spike Noise Suppressed by Input Filter tSP
0
-
Note 29. I²C is a registered trademark of Philips Semiconductors.
TVDD voltage must be 2.7V ∼ 3.6V in I²C mode.
Note 30. Data must be held long enough to bridge the 300ns-transition time of SCL.
max
Units
400
kHz
-
µs
-
µs
-
µs
-
µs
-
µs
-
µs
-
µs
0.3
µs
0.3
µs
-
µs
400
pF
50
ns
MS0506-E-02
- 12 -
2006/07