AK4342 Datasheet, PDF (22/43 Pages) Asahi Kasei Microsystems – 24-Bit Stereo DAC with HP-AMP & 2V Line-Out

ASAHI KASEI
[AK4342]
„ Charge Pump Circuit
The internal charge pump circuit generates negative voltage from PVDD voltage. The generated voltage is used to lineout
and headphone amplifiers. When PMCP bit is set to “1”, the charge pump circuit is powered-up. Then all clocks (MCLK,
BICK and LRCK) should be supplied. The power up time of charge pump circuit depends on FS3-0 bits (See Table 9).
FS3 bit
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FS2 bit FS1 bit FS0 bit
Sampling
Frequency
Power up time of
Charge Pump
Circuit
0
0
0
44.1kHz
11.6ms
0
0
1
32kHz
8.0ms
0
1
0
48kHz
10.7ms
0
1
1
(Reserve)
(Reserve)
1
0
0
88.2kHz
11.6ms
1
0
1
64kHz
8.0ms
1
1
0
96kHz
10.7ms
1
1
1
(Reserve)
(Reserve)
0
0
0
22.05kHz
11.6ms
0
0
1
16kHz
8.0ms
0
1
0
24kHz
10.7ms
0
1
1
(Reserve)
(Reserve)
1
0
0
11.025kHz
11.6ms
1
0
1
8kHz
8.0ms
1
1
0
12kHz
10.7ms
1
1
1
(Reserve)
(Reserve)
Table 9. Power up time of Charge Pump Circuit
Default
„ Analog Input
Signal level from LIN/RIN is adjusted by an external resistor (Ri). Internal feedback resistance (Rf) is 20k ± 30% Ω.
When PMDAC, PMHP, PMLO or PMAUX bit is set to “1”, the left and right channel amplifiers are powered-up. The
transition time of signal path (LINL, LINR, RINL and RINR bits) is selected by PTS1-0 bits and FS3-0 bits. The signal
path (LINL, LINR, RINL and RINR bits) should not be changed during the transition.
Rf = 20kΩ
Ri
LIN/RIN
-
+
Figure 17. Block diagram of LIN/RIN inputs
MS0506-E-02
- 22 -
2006/07