AK4544A Datasheet, PDF (3/35 Pages) Asahi Kasei Microsystems – AC97 MULTIMEDIA AUDIO CODEC WITH SRC

[ASAHI KASEI]
[AK4544A]
No. Signal Name
1 DVdd1
2 XTL_IN
(MCLKI)
3 XTL_OUT(open)
4 DVss1
5 SDATA_OUT
6 BIT_CLK
7 DVss2
8 SDATA_IN
9 DVdd2
10 SYNC
11 RESET#
12 PC_BEEP
13 PHONE
14 AUX_L
15 AUX_R
16 VIDEO_L
17 VIDEO_R
18 CD_L
19 CD_GND
20 CD_R
21 MIC1
22 MIC2
23 LINE_IN_L
24 LINE_IN_R
25 AVdd1
26 AVss1
27 Vref
28 VrefOut
29 AFILTL
30 AFILTR
31 VRAD
32 PLLfilter
33 VRDA
34 3Dcap
35 LINE_OUT_L
36 LINE_OUT_R
37 MONO_OUT
38 AVdd2
39 LNLVL_OUT_L
40 NC
41 LNLVL_OUT_R
42 AVss2
43 TEST2
44 TEST3
45 Codec ID0#
46 Codec ID1#
Pin/Function
I/O
Description
- Digital power supply; 3.3V or 5.0V(DVdd1 = DVdd2)
0.1uF + 4.7uF capacitors should be connected to digital ground.
I 24.576MHz(512fs) Crystal is normally connected.
If crystal is not connected, external clock can be used.
O 24.576MHz(512fs) Crystal. If external clock is used, this pin should be open.
- Digital Ground; 0V. This pin should be directly connected to DVss2 on board.
I Serial 256-bit AC’97 data stream from digital controller
I/O 12.288MHz(256fs) serial data clock
Output at Primary codec. Input at Secondary codec.
- Digital Ground; 0V. This pin should be directly connected to DVss1 on board.
O Serial 256-bit AC’97 data stream to digital controller
- Digital power supply; 3.3V or 5.0V(DVdd1 = DVdd2)
0.1uF + 4.7uF capacitors should be connected to digital ground.
I AC’97 Sync Clock, 48kHz(1fs) fixed rate sampling rate
I AC’97 Master Hardware Reset
I PC Speaker beep pass through
I From telephony subsystem speakerphone
I Aux Left Channel
I Aux Right Channel
I Video Audio Left Channel
I Video Audio Right Channel
I CD Audio Left Channel
I CD Audio analog ground
CD_GND or analog ground should be connected through capacitor.
I CD Audio Right Channel
I Desktop Microphone Input
I Second Microphone Input
I Line In Left Channel
I Line In Right Channel
- Power supply; 5.0V(AVdd1=AVdd2)
0.1uF + 4.7uF capacitors should be connected to AVss1(analog ground).
- Analog Ground; 0V
O Reference Voltage Output;
0.1µF +4.7µF capacitors should be connected to Avss1(analog ground).
O Reference Voltage Output (2.5V,1.25mA)
O Anti-Aliasing Filter Cap; Connected to analog ground with 1nF capacitor.
O Anti-Aliasing Filter Cap; Connected to analog ground with 1nF capacitor.
O Vref for ADC ; 0.1µF capacitor should be connected to analog ground.
O Loop filter for PLL is connected; 36k resistor and 33nF capacitor in series and
390pF capacitor.
O Vref for DAC; 0.1µF capacitor should be connected to analog ground.
O 3D Enhancement Cap; 27nF capacitor should be connected to analog ground.
O Line Out Left Channel
O Line Out Right Channel
O To telephony subsystem speakerphone
- Power supply; 5.0V(AVdd1=AVdd2)
0.1uF capacitor should be connected to AVss2(analog ground).
O True Line Level Out Left Channel
- No Connection
O True Line Level Out Right Channel
- Analog Ground
I Test pin (This pin should be open for normal operation):With internal pull-down.
I Test pin (This pin should be open for normal operation):With internal pull-down.
I Codec ID configuration(ID select input for multiple codec extension) See Page21.
Negative logic input. With internal pull-up.
I Codec ID configuration(ID select input for multiple codec extension) See Page21.
Negative logic input. With internal pull-up.
<MS0026-E-00>
-3-
2000/04