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AK4544A Datasheet, PDF (13/35 Pages) Asahi Kasei Microsystems – AC97 MULTIMEDIA AUDIO CODEC WITH SRC | |||
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[ASAHI KASEI]
[AK4544A]
Slot
0
1
2
3
4
5
6
7
8
9
10
11
12
SYNC
Codec ID1:Codec ID0=0:0 or 0:1
SDATA
TAG Command Command PCM(dac) PCM(dac) All
All
All
All
All
All
All
All
OUT
Address Data
Left
Right
â0â
â0â
â0â
â0â
â0â
â0â
â0â
â0â
Codec ID1:Codec ID0=1:0
TAG Command Command All
All
All
All
PCM(dac) PCM(dac)
All
All
All
All
Address Data
â0â
â0â
â0â
â0â
Left
Right
â0â
â0â
â0â
â0â
Codec ID1:Codec ID0=1:1
PCM(dac) PCM(dac)
All
All
TAG Command Command All
All
All PCM(dac)
All
All
PCM(dac)
All
All
All
Address Data
â0â
â0â
â0â
Left
â0â
â0â
Right
â0â
â0â
â0â
PCM(dac) PCM(dac)
All
SDATA
TAG
Status Status PCM(adc) PCM(adc) All
All
All
All
All
All
All
All
IN
Address Data
Left
Right
â0â
â0â
â0â
â0â
â0â
â0â
â0â
â0â
Tag Phase
Data Phase
48kHz
AC-link protocol identifies 13slots of data per frame. The frequency of sync is fixed to 48kHz. Only Slot 0, which is
the Tag phase, is 16bits, all other slots are 20bits in length. These slots are explained in later sections.
AC-link Audio Output Frame (SDATA_OUT)
a)Slot 0
Primary codec(CodecID1:CodecID0=0:0)
SYNC
BIT_CLK
SDATA_OUT
Valid
Frame
Slot1
Slot2
Slot3
Slot4 Slot5 Slot6 Slot7 Slot8 Slot9
Slot10 Slot11 Slot12
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9â Bit8 Bit7â Bit6â Bit5â Bit4 Bit3 Bit2 Bit1 Bit0
ââ1/0â ââ1/0â ââ1/0â ââ1/0â ââ1/0â â â0â â0â ââ0â â0â â0â â0â ââ0â â0â ââ0â
â0â
â0â
1 BIT_CLK delay
Slot 0
Slot 1
Secondary codec (CodecID1:CodecID0 = 0:1 or 1:0 or 1:1)
SYNC
BIT_CLK
SDATA_OUT
1 BIT_CLK delay
Valid
Frame
Slot1
Bit15 Bit14
ââ1/0â ââ0â
Slot2 Slot3 Slot4
Bit13 Bit12 Bit11
ââ0â ââ1/0â ââ1/0â
Slot5
Bit10
ââ0â
Slot6 Slot7 Slot8 Slot9
Bit9â Bit8 Bit7â Bit6â
â1/0â ââ1/0â â1/0â â1/0â
Slot10 Slot11 Slot12
Bit5â Bit4 Bit3 Bit2
â0â ââ0â â0â ââ0â
Slot 0
Bit1 Bit0
â1/0â â1/0â
Slot 1
The AK4544A checks bit15 (valid frame bit). Note that when the valid frame bit is â1â, at least one bit14-6 (slot 1-9)
or bit1-0 must be valid, bit5-2 will be â0âand should be ignored.
If bit15 is â0â, the AK4544A ignores all following information in the frame.
The AK4544A then checks the validity of each bit in the TAG phase (slot 0).
If each bit is â0â, the AK4544A ignores the slot indicated by â0â. On the other hand, if each bit is â1â, the slot is valid.
All bits in slot10-12(bit5-3) are â0â and bit2 is also â0â.
The AK4544A monitors bit1 and 0, which are codec ID configuration bits used in multiple codec designs. These bits
are used to identify which codec the frame data is issued to.
<MS0026-E-00>
- 13 -
2000/04
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