AK4544A Datasheet, PDF (16/35 Pages) Asahi Kasei Microsystems – AC97 MULTIMEDIA AUDIO CODEC WITH SRC

[ASAHI KASEI]
[AK4544A]
AC-link Input Frame(SDATA_IN)
Each AC-link frame consists of one 16bit tag phase and twelve 20bit slots used for data and control.
a) Slot0
Slot0 is a special time frame, and consists of 16bits. Slot0 is also named the Tag phase. The AK4544A supports Bits
15-11 and bits1-0. Each bit indicates “1”=valid(normal operation) or ready, “0”=invalid(abnormal operation) or not
ready.
If the first bit in the slot 0 (Bit15) is valid, the AK4544A is ready for normal operation. ³If the “Codec Ready” bit is
invalid, the following bits and remaining slots are all “0”. AC’97 controller should ignore the following bits in the
slot 0 and all other slots. When the ADC sampling rate is set for less than 48kHz, then Bits 12and 11 in slot 0
( corresponds to slot3 and slot4 respectively ) will be 1’s when valid data is transferred in SDATA_IN, and will be 0’s
when no data is transmitted. ( On-demand ) base data transaction )
The next is the extracted description from AC’97 Rev.2.1 ;
“For variable sample rate input, the tag bit for each input slot indicates whether valid data is present or not. Thus,
even in variable sample rate mode, the Codec is always the master: for SDATA_IN (Codec to Controller), the Codec
sets the TAG bit; for SDATA_OUT (Controller to Codec), the Codec sets the SLOTREQ bit and then checks for the
TAG bit in the next frame.” AK4544A expects Controller will reply TAG bit in the next frame correctly.
Bit 14 means that Slot 1(Status Address) output is valid or invalid. And Bit 13 means that Slot 2(Status Data) is
valid or invalid.
The following table shows the relationship between Bit 14,13 and each Status of the AK4544A.
Bit 15
Bit 14
Bit 13
Status
(CodecReady) (StatusAddress) (StatusData)
1
1
1
There is a Read Command in the previous frame.
Then both Slot 1 and Slot 2 output normal data.
If the access to non-implemented register or odd register is requested, the
AK4544A returns “valid” 7-bit register address in slot 1 and returns
“valid”0000h data in slot 2 on the next AC-link frame.
1
1
0
Prohibited or non-existing
1
0
0
There is no Read Command in the previous frame.
Bits 19-12, Bit 9 and Bits 4-0 in Slot 1 are set to ”0”. And Slot2 outputs All”0”.
1
0
1
Prohibited or non-existing
Note 1). The above Read sequence is done as response for previous frames read command. That is, if the previous
frame is the Write Command, AK4544A outputs bit14 =”0”, bit13 =”0” and slot 1&2 = All”0”, if there is no
SLOTREQ.
2). The Bits 14 and 13 in Slot 0 is independent of the SLOTREQ Bits 11,10, 8, 7, 6 and 5 in Slot 1 which the
AK4544A supports.
Bit12 means the output of Slot 3(PCM(ADC) Left) is valid or invalid. And Bit 11 means the output of Slot
4(PCM(ADC)Right) is valid or invalid. Bits10-0 are occupied with “0”.
A new audio input frame begins with a low to high transition of SYNC. SYNC is synchronous to the rising edge of BIT_CLK. On the
immediately following falling edge of BIT_CLK, the AK4544A samples the assertion of SYNC. This falling edge marks the time
when both sides of AC-link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the AK4544A transitions
SDATA_IN into the first bit position of slot 0 (“Codec Ready” bit). Each new bit position is presented to AC-link on a rising edge of
BIT_CLK, and subsequently sampled by the AC ’97 controller on the following falling edge of BIT_CLK. This sequence ensures that
data transitions, and subsequent sample points for both incoming and outgoing data streams are time aligned.
SYNC
BIT_CLK
SDATA_IN
Codec
Ready
Slot1 Slot2 Slot3
Slot4 Slot5 Slot6 Slot7 Slot8
“1/0” “1/0” “1/0” “1/0” “1/0” “0” “0” “0” “0”
Bit15Bit14 Bit13 Bit1_S2_loB_tit₀11 Bit10 Bit9 Bit8 Bit7
Slot11 Slot12
“0” “0” “0” “0” “0”
Bit4 Bit3 Bit2 Bit1 Bit0
Slot 1
3 _{When the AC’ 97 is not ready for normal operation, output bits are not specified and should be ignored.}
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2000/04