AK4544A Datasheet, PDF (27/35 Pages) Asahi Kasei Microsystems – AC97 MULTIMEDIA AUDIO CODEC WITH SRC

[ASAHI KASEI]
[AK4544A]
PR0=1
PR1=1
PR4=1
Normal
ADCs off
PR0
DACs off
PR1
Digital
I/F
off
PR4
PR0=0
&
ADC=1
PR1=0
&
DAC=1
Warm Reset
AK4544A Powerdown/Powerup flow with analog still alive
Shut off
AC-Link
nPowerdown/Powerup sequence of Multiple codec configuration
Under the multiple codec circumstances, there is no restriction on setting PR0(ADC), PR1(DAC), PR2(Mixer),
PR6(LNLVL_OUT) and PR7(EAPD) to “1” or “0”.
As suggested in AC’97 Specification Rev2.1, AC-Link Powerdown(PR”4”) and Vref Powerdown(PR5=”1”) under
the Multiple codec configuration are NOT recommended in order to continue supplying BIT_CLK to Secondary
codecs.
Below table shows the relationship for AC-Link Powerdown/Powerup procedure.
AC-LinkPowerdownProcedure SubsequentProcedureforPowerup Comments
RESET#=L
Cold Reset
Cold Reset wakes up all of codecs with default register
setting concurrently.
Shutdown(CompletePowerdown) ColdReset
Cold Reset wakes up all of codecs with default register
setting concurrently.
Note:
1) The AC-Link Powerdown of Primary AC’97 will stop supplying the BIT_CLK to the Secondary AC’97.
2) When the AC-Link Powerdown is issued to the Secondary of AC’97, the Secondary of AC’97 will go to the AC-
Link Powerdown and Warm Reset will be followed by Syn signal at the next time frame.
nTestability
Activating the Test Modes
AC ‘97 has two test modes. One is for ATE in circuit test and the other is for vendor specific tests. AC ‘97 enters the ATE in circuit
test mode regardless of SYNC signal (high or low) if SDATA_OUT is sampled high at the trailing edge of RESET#. AC ‘97 enters
AKM test mode in the case of condition below. These cases will never occur during standard operating conditions.
Regardless of the test mode, the AC ‘97 controller must issue a “Cold” reset to resume normal operation of the AC ‘97 Codec.
Test Mode Functions
ATE in circuit test mode
When AC ‘97 is placed in the ATE test mode, its digital AC-link outputs (i.e. BIT_CLK and SDATA_IN) are driven to a high
impedance state. This allows ATE in circuit testing of the AC ‘97 controller.
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