AK4213 Datasheet, PDF (27/38 Pages) Asahi Kasei Microsystems – Mono Class-D SPK-Amp with Stereo Cap-less HP-Amp

[AK4213]
■ Serial Control Interface
The AK4213 supports a fast-mode I²C-bus system (max: 400kHz). Pull-up resistors at the SCL and SDA pins should be
connected to (TVDD + 0.3)V or less voltage.
1. WRITE Operations
Figure 20 shows the data transfer sequence for the I²C-bus mode. All commands are preceded by START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates START condition (Figure 26). After the START
condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit (R/W).
The most significant seven bits of the slave address are fixed as “0010011”(Figure 21). If the slave address matches that
of the AK4213, the AK4213 generates an acknowledge and the operation is executed. The master must generate the
acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 27). An
R/W bit value of “1” indicates that the read operation is to be executed. “0” indicates that the write operation is to be
executed.
The second byte consists of the control register address of the AK4213. The format is MSB first, and those most
significant 3-bit are fixed to zero (Figure 22). The data after the second byte contains control data. The format is MSB
first, 8bits (Figure 23). The AK4213 generates an acknowledge after each byte is received. A data transfer is always
terminated by STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH
defines STOP condition (Figure 26).
The AK4213 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4213
generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the
write cycle after the first data byte is transferred. After receiving each data packet the internal 5-bit address counter is
incremented by one, and the next data is automatically taken into the next address. If the address exceeds 12H prior to
generating the stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data
line can only change when the clock signal on the SCL line is LOW (Figure 28) except for the START and STOP
conditions.
S
T
A
R/W="0"
R
T
SDA
Slave
S _Address
Sub
Address(n)
A
A
C
C
K
K
Data(n)
Data(n+1)
A
A
C
C
K
K
Figure 20. Data Transfer Sequence
S
T
O
P
Data(n+x)
P
A
A
C
C
K
K
0
0
1
0
0
1
1
R/W
Figure 21. The First Byte
0
0
0
A4
A3
A2
A1
A0
Figure 22. The Second Byte
D7
D6
D5
D4
D3
D2
D1
D0
Figure 23. Byte Structure after the second byte
MS0949-E-01
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2008/07