AK4213 Datasheet, PDF (19/38 Pages) Asahi Kasei Microsystems – Mono Class-D SPK-Amp with Stereo Cap-less HP-Amp

[AK4213]
(3) Example of ALC Operation
Table 11 shows the example of the ALC setting. The ALC starts from the value of SPGA5-0 bits.
Register Name
LMTH
ZELMN
WTM2-0
REF5-0
LMAT1-0
RGAIN1-0
ZTM1-0
ALC
Comment
Data
Parameter
Limiter detection Level
0
−7.5dBV
Limiter Zero crossing Enable
0
Limiter Zero Crossing Enable
Recovery waiting period
101
typ. 524.8ms
Maximum gain at recovery operation 3CH
+18dB
Limiter ATT Step
00
0.5dB
Recovery GAIN Step
00
0.5dB
Zero-crossing Timeout
01
typ. 32.8ms
ALC Enable bit
1
Enable
Table 11. Example of the ALC setting
The following registers should not be changed during the ALC operation. These bits should be changed after the ALC
operation is finished by ALC bit = “0”.
- LMTH, LMAT1-0, WTM2-0, RGAIN1-0, REF5-0, ZTM1-0 and ZELMN bits
ALC=OFF
Example:
Limiter: Zero Crossing Enable
Recovery Cycle = typ. 524.8ms
Limiter and Recovery Step = 1
Maximum Gain = +18dB
Limiter Detection Level = −7.5dBV
ALC bit = “1”
WR (SPGA5-0)
WR (REF5-0)
* The value of SPGA should be
the same or smaller than REF’S.
(1) Addr=0EH, Data=3CH
(2) Addr=0FH, Data=3CH
WR (ZTM1-0, WTM2-0)
(3) Addr=10H, Data=0DH
WR (ZELMN, LMAT1-0, RGAIN1-0, LMTH, ALC=”1”)
(4) Addr =11H, Data=40H
ALC Operation
Note: WR: Write
Figure 13. Registers set-up sequence at ALC operation
MS0949-E-01
- 19 -
2008/07