AK4213 Datasheet, PDF (20/38 Pages) Asahi Kasei Microsystems – Mono Class-D SPK-Amp with Stereo Cap-less HP-Amp

[AK4213]
■ Speaker Volume (SPGA: Manual Mode)
The speaker volume becomes manual mode when ALC bit is “0”. This mode is used in the case shown below.
1. Set-up the registers for the ALC operation (ZTM1-0, LMTH and etc).
2. Set-up the initial value of SPGA when ALC starts.
3. When SPGA is used as a manual volume.
SPGA5-0 bits set the gain of the volume control. The SPGA value is changed at zero crossing or timeout. Zero crossing
timeout period is set by ZTM1-0 bits. When PMSPK bit is “0”, SPGA5-0 bits does not write to anything. After PMSPK
bit is changed from “0” to “1”, writing to SPGA5-0 bits is inhibit within 1.6ms.
When changing from PMSPK bit = “0” to PMSPK bit = “1”, SPGA volume becomes default value (0dB) regardless of the
setting of SPGA5-0 bits.
SPGA5-0 bits
GAIN (dB)
Step
3FH
+19.5
3EH
+19.0
3DH
+18.5
3CH
+18.0
:
:
19H
+0.5
0.5dB
18H
0.0
17H
−0.5
:
:
02H
−11.0
01H
−11.5
00H
−12.0
Table 12. Speaker-Amp Volume Setting
(default)
When writing to the SPGA5-0 bits continuously, the control register should be written with an interval more than zero
crossing timeout.
ALC bit
ALC Status
Disable
Enable
Disable
SPGA5-0 bits
3CH(+18dB)
Internal SPGA
3CH(+18dB)
3CH(+18dB) --> 19H(+0.5dB)
(1)
3CH(+18dB)
(2)
Figure 14. SPGA value during ALC operation
(1) ALC operation starts from the SPGA value when ALC bit is changed to “1”.
(2) Writing to SPGA registers is ignored during ALC operation. After ALC is disabled, the SPGA changes to the last
written data by twice period of zero crossing or timeout. When ALC is enabled again, ALC bit should be set to “1” in
an interval more than zero crossing timeout period after ALC bit = “0”.
MS0949-E-01
- 20 -
2008/07