AK4631 Datasheet, PDF (24/69 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK-AMP

ASAHI KASEI
[AK4631]
PLL2 bit = “0” ͷ৔߹(FCK or BICKΑΓೖྗ)͸ɺFS3, FS1-0 bitͰαϯϓϦϯάप೾਺ͷઃఆΛߦͬͯԼ͞
͍ʢTable 6ʣɻ
Mode FS3 bit FS2 bit FS1 bit FS0 bit Sampling Frequency Range
0
0
Don’t care
0
0
7.35kHz ≤ fs ≤ 8kHz
1
0
Don’t care
0
1
8kHz < fs ≤ 12kHz
2
0
Don’t care
1
0
12kHz < fs ≤ 16kHz
3
0
Don’t care
1
1
16kHz < fs ≤ 24kHz
6
1
Don’t care
1
0
24kHz < fs ≤ 32kHz
7
1
Don’t care
1
1
32kHz < fs ≤ 48kHz
Others
Others
N/A
Table 6. Setting of Sampling Frequency at PLL2 bit = “0” and PMPLL bit = “1”
Default
(Note) FCK ج४(PLL3-0 bits = “0000”) ͷ৔߹ͷαϯϓϦϯάप೾਺͸ 7.35kHz ≤ fs ≤ 26kHz Ͱ͢ɻ
„ PLL ͷΞϯϩοΫʹ͍ͭͯ
1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
͜ͷϞʔυͰ PMPLL bit = “0” Æ “1”ޙͨ͠ʹɺ͋Δ͍͸αϯϓϦϯάप೾਺Λมߋͨ͠৔߹ɺFCK, BICK,
MCKO͔Β͸ਖ਼ৗͰͳ͍प೾਺ͷΫϩοΫ͕ग़ྗ͞Ε·͢ɻͦͷޙɺPLL͕ΞϯϩοΫΛݕग़ͨ͠৔߹ɺΞ
ϯϩοΫʹͳͬͨॠؒɺFCKͱBICKग़ྗ͸੍ڧతʹ “L”ʹͳΓ·͕͢ɺMCKO bit = “1”ͷ৔߹ɺMCKO͔Β
͸ਖ਼ৗͰͳ͍ΫϩοΫ͕ग़ྗ͞Ε·͢ɻMCKO bit = “0”ͷ৔߹͸ɺMCKO͸ “L”Λग़ྗ͠·͢ɻ(See Table 7)
PLL ϩοΫޙɺBICKͱFCKग़ྗ͸ “L”͔ΒΫϩοΫग़ྗͱͳΓ·͢ͷͰ࠷ॳͷ1पظ෼ͷFCK, BICK͸ɺਖ਼
ৗͰͳ͍Մೳੑ͕͋Γ·͕͢ɺ1fsʹޙ͸ਖ਼ৗͳΫϩοΫʹͳΓ·͢ɻ
PLL State
MCKO pin
MCKO bit = “0” MCKO bit = “1”
PMPLL bit “0” Æ “1”௚ޙ
“L” Output
ෆఆ
BICK pin
ෆఆ
FCK pin
ෆఆ
PLL Unlock ݕग़࣌
“L” Output
ෆఆ
“L” Output
“L” Output
PLL Lock ࣌
“L” Output
256fs Output
See Table 9
1fs Output
Table 7. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
͜ͷϞʔυͰ͸ PMPLL bit = “0” Æ “1”ޙͨ͠ʹɺ͋Δ͍͸αϯϓϦϯάप೾਺Λมߋͨ͠৔߹ɺMCKO͔Β
͸ਖ਼ৗͰͳ͍प೾਺ͷΫϩοΫ͕ग़ྗ͞Ε·͢ɻͦͷޙɺPLL͕ϩοΫ͢ΔͱMCKO͔Β256fsͷΫϩοΫ͕
ग़ྗ͞Ε·͢ɻୠ͠ɺPLL͕ΞϯϩοΫʹͳͬͨ৔߹ɺADCͼٴDAC͔Β͸ਖ਼ৗͳσʔλ͕ग़ྗ͞Ε·ͤΜɻ
DACʹؔͯ͠͸ɺAddr=02HͷDACA bit ͱ DACM bit Λ “0”ʹ͢Δ͜ͱʹΑΓग़ྗΛϛϡʔτ͢Δ͜ͱ͕Մೳ
Ͱ͢ɻ
PLL State
PMPLL bit “0” Æ “1”௚ޙ
MCKO pin
MCKO bit = “0” MCKO bit = “1”
“L” Output
ෆఆ
PLL Unlock ݕग़࣌
“L” Output
ෆఆ
PLL Lock ࣌
“L” Output
256fs Output
Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
MS0317-J-01
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2004/11