AK4631 Datasheet, PDF (12/69 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK-AMP

ASAHI KASEI
[AK4631]
εΠονϯάಛੑ
(Ta = 25°C; AVDD, DVDD =2.6 ∼ 3.6V, SVDD =2.6 ∼ 5.25V; C_L=20pF)
Parameter
Symbol
min
PLL Master Mode (PLL Reference Clock = MCKI pin) (Figure 2)
MCKI Input: Frequency
fCLK
11.2896
Pulse Width Low
tCLKL
0.4/fCLK
Pulse Width High
tCLKH
0.4/fCLK
MCKO Output:
Frequency
fMCK
Duty Cycle except fs=29.4kHz,32kHz
dMCK
40
fs=29.4kHz, 32kHz (Note 23) dMCK
FCK Output: Frequency
fFCK
8
Duty Cycle
dFCK
BICK: Period (BCKO1-0 = “00”)
tBCK
(BCKO1-0 = “01”)
tBCK
(BCKO1-0 = “10”)
tBCK
Duty Cycle
dBCK
Audio Interface Timing
DSP Mode: (Figure 3, Figure 4)
FCK “↑” to BICK “↑” (Note 24)
FCK “↑” to BICK “↓” (Note 25)
BICK “↑” to SDTO (BCKP = “0”)
BICK “↓” to SDTO (BCKP = “1”)
tDBF
tDBF
tBSD
tBSD
0.5 x tBCK -40
0.5 x tBCK -40
-70
-70
SDTI Hold Time
tSDH
50
SDTI Setup Time
tSDS
50
Except DSP Mode: (Figure 5)
BICK “↓” to FCK Edge
tBFCK
-40
FCK to SDTO (MSB) (Except I²S
tFSD
-70
mode)
BICK “↓” to SDTO
tBSD
-70
SDTI Hold Time
tSDH
50
SDTI Setup Time
tSDS
50
typ
256 x fFCK
50
33
50
1/16fFCK
1/32fFCK
1/64fFCK
50
0.5 x tBCK
0.5 x tBCK
max
27.0
60
48
Units
MHz
ns
ns
kHz
%
%
kHz
%
ns
ns
ns
%
0.5 x tBCK + 40 ns
0.5 x tBCK +40 ns
70
ns
70
ns
ns
ns
40
ns
70
ns
70
ns
ns
ns
MS0317-J-01
- 12 -
2004/11