AK4133VN Datasheet, PDF (22/28 Pages) Asahi Kasei Microsystems – 192kHz 24bit Sample Rate Converter

[AK4133]
▪ When the frequency of OLRCK at output port is changed without a reset by the PDN pin
When the difference of internal oscillator clock number in one OLRCK cycle between before and after
changing OLRCK frequency (FSO/FSI ratio should be stabilized) is more than 1/16 for 8cycles (*), an
internal reset is made automatically and sampling frequency ratio detection is executed again. SDTO
outputs “L” when the internal reset is made, and SRC data is output after 162FSI(O) (FSI(O) is lower
frequency between FSI and FSO).
When the above condition (*) is not satisfied, the internal reset mentioned before will not be executed.
It takes 5148/FSO (max. 643.5ms@FSO=8kHz) (* 18) to output normal SDTO data. Distorted data may
be output until normal SDTO output.
When OLRCK is stopped, an internal reset is executed automatically. It takes 162FSI(O) (FSI(O) is lower
frequency between FSI and FSO) [sec] to output normal SDTO data after ILRCK is input again.
Notes:
* 18. When FSO=8kHz and FSO/FSI ratio is changed from 1/6 to 1/5.99.
■ Internal Status Pin
The SRCE_N pin outputs internal state of the device. It outputs “H” while the PDN pin = “L”.
SRC data is output from the SDTO pin when the PDN pin = “H” and the sampling frequency ratio
detection is completed if the internal regulator is operated normally.
An internal limit flag is set when an over current or over voltage flows at the internal regulator. An ORed
result of the internal limit flag and an inverted flag of the ratio detection completion of SRC is output from
the SRCE_N pin.
Limit Flag at Regulator
“L” Normal Operation
“H” Over Current (Voltage) Detect
Ratio Detection End Flag at SRC
SRCE_N Pin
Figure 19. Internal Flag and SRCE_N Pin Output
■ Grounding ans Power Supply Decoupling
The AK4133 requires careful attention to power supply and grounding arrangements. Decoupling
capacitors should be placed as near as possible to the supply pins.
015015325-E-01
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2016/06