AK4133VN Datasheet, PDF (21/28 Pages) Asahi Kasei Microsystems – 192kHz 24bit Sample Rate Converter

[AK4133]
■ Clock Switch Sequence
The AK4133 must be reset by bringing the PDN pin to “L” when changing operation clocks. Clock
change sequence is shown in Figure 18.
External clocks
(input port
or output port)
Clocks 1
(Don’t care) Clocks 2
PDN
(1)
(4)
< 25.2ms
(Internal state) normal operation ^Power
down
LDO up & Ratio
detection & GD
SDTO
normal data
(2)
(2)
normal operation
normal data
SMUTE
0dB
Att.Level
-dB
(3)
1024/fso
(5) ^1024/fso
Figure 18. Clock Change Sequence
(1) Set the PDN pin to “L”, and change clock frequencies of the IDIF pin, ODIF pin and CM1-0 pins.
(2) Click noise may occur when the STDO output is changed.
(3) Mute the SDTO output by setting the SMUTE pin to “H” before setting the PDN pin to “L” if the click
noise influences system applications. This click noise can also be prevented by setting “0” to the
SDTI from GD before the PDN pin changes to “L”. It makes the data on SDTO remain as “0”.
(4) Set the PDN pin to “H” after changing the clock of the IDIF pin, ODIF pin or CM1-0 pins.
(5) Set the SMUTE pin to “L” to release the soft mute if the soft mute function is enabled.
The AK4133 has automatic internal reset function for when ILRCK or OLRCK frequency is changed. The
behavior of the device when ILRCK or OLRCK frequency is changed is shown below.
▪ When the frequency of ILRCK at input port is changed without a reset by the PDN pin.
When the difference of internal oscillator clock number in one ILRCK cycle between before and after
changing ILRCK frequency (FSO/FSI ratio should be stabilized) is more than 1/16 for 8cycles (*), an
internal reset is made automatically and sampling frequency ratio detection is executed again.
The SDTO pin outputs “L” when the internal reset is made, and SRC data is output after 162FSI(O)
(FSI(O) is lower frequency between FSI and FSO).
When the above condition (*) is not satisfied, the internal reset mentioned before will not be executed.
It takes 5148/FSO (max. 643.5ms@FSO=8kHz) (* 18) to output normal SRC data. Distorted data may
be output until normal SRC output.
When ILRCK is stopped, an internal reset is executed automatically. It takes 162FSI(O) (FSI(O) is lower
frequency between FSI and FSO) to output normal SRC data after ILRCK is input again.
015015325-E-01
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2016/06