AK4133VN Datasheet, PDF (11/28 Pages) Asahi Kasei Microsystems – 192kHz 24bit Sample Rate Converter

[AK4133]
■ Timing
(Ta=-40 +105C; DVDD=3.03.6V at VSEL pin=”L” or DVDD=VD18=1.7V1.9V at VSEL pin=”H”;
C_L=20pF)
Parameter
Symbol
Min.
Typ. Max Unit
Audio Interface Timing
Input PORT
IBICK Period Normal speed Mode
Double speed Mode
Quad speed Mode
IBICK Pulse Width Low
IBICK Pulse Width High
ILRCK Edge to IBICK “↑” (* 13)
IBICK “↑” to ILRCK Edge (* 13)
SDTI Hold Time from IBICK “↑”
SDTI Setup Time to IBICK “↑”
tIBCK 1/256 FSIN
-
tIBCK 1/128 FSID
-
tIBCK
1/64 FSIQ
-
tIBCKL
27
-
tIBCKH
27
-
tILRB
15
-
tIBLR
15
-
tISDH
15
-
tISDS
15
-
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
Output PORT (Slave Mode)
OBICK Period Normal speed Mode
tOBCK 1/256 FSON
-
OBICK Pulse Width Low
tOBCKL
27
-
OBICK Pulse Width High
tOBCKH
27
-
OLRCK Edge to OBICK “↑” (* 13)
tOLRB
20
-
OBICK “↑” to OLRCK Edge (* 13)
tOBLR
20
-
OLRCK to SDTO(MSB) (Except I²S Mode) tOLRS
-
-
OBICK “↓” to SDTO
tOBSD
-
-
-
ns
-
ns
-
ns
-
ns
-
ns
20
ns
20
ns
Output PORT (Master Mode)
OBICK Frequency
OBICK Duty
OBICK “↓” to OLRCK Edge
OBICK “↓” to SDTO
fOBCK
-
64 FSO -
Hz
dOBCK
-
50
-
%
tOMBLR
-20
-
20
ns
tOBSD
-20
-
20
ns
Reset Timing
PDN Pulse Width (* 14)
tPD
150
-
-
ns
PDN pin Pulse Width of Spike Noise
Suppressed by Input Filter (* 15)
tPDS
0
-
50
ns
Notes:
* 13. BICK rising edge must not occur at the same time as LRCK edge.
* 14. The AK4133 can be rest by bringing the PDN pin = “L”.
* 15. Spike noise width of “L” pulse suppressed by input filter of the PDN pin.
015015325-E-01
- 11 -
2016/06