AK4133VN Datasheet, PDF (19/28 Pages) Asahi Kasei Microsystems – 192kHz 24bit Sample Rate Converter

[AK4133]
■ System Reset
Bringing the PDN pin = “L” sets the AK4133 power-down mode and initializes the digital filters. The
AK4133 should be reset once by bringing the PDN pin to “L” upon power-up. The internal SRC circuit is
powered-up on ILRCK and OLRCK input after a power-up period of the internal regulator (PDN pin =
“H”). The data output time of the SDTO pin depends on the LRCK and OLRCK input when the PDN pin =
“H”. (Figure 16, Figure 17)
Case 1: ILRCK and OLRCK are input when the PDN pin= “H”
Case 1
External clocks
(Input port) ^{Don’t care}
SDTI
Don’t care
External clocks
(Output port)
Don’t care
Input Clocks 1
Input Data 1
Output Clocks 1
PDN
(1)
(2)
(3)
< 25.2ms
(Internal state) Power-down
LDO Up& Ratio
detection & GD
Normal
operation
Input Clocks 2
Don’t care
Input Data 2
Don’t care
Output Clocks 2
(4)
Don’t care
(2)
(3)
< 25.2ms
PD
LDO Up& Ratio
detection & GD
Normal
operation
Power-down
SDTO
“0” data
Normal data
“0” data
Normal data “0” data
SRCE_N
Figure 16. System Reset Case1
LDO: Internal Regurator
GD: Group Delay
PD: Power Down
(1) The SDTO pin outputs “L” and the SRCE_N pin outputs “H” when the PDN pin= “L”.
(2) The Internal regulator is powered up by bringing the PDN pin = “H” after operation clock is input.
Then, SRC circuit is powered up and starts Ratio detection by ILRCK and OLTCK. SDTO is output
after group delay period when Ratio detection is completed. Until then the SDTO outputs “L” and the
SRCE_N pin outputs “H”. The time until SDTO output become enabled after setting the PDN pin to
“H” is 25.2msec (Max.).
(3) The SRCE_N pin outputs “L” when SDTO data output becomes enabled.
(4) The statuses of the CM1-0, ODIF and IDIF pins should be changed while the PDN pin= “L”.
015015325-E-01
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2016/06