AK4133VN Datasheet, PDF (20/28 Pages) Asahi Kasei Microsystems – 192kHz 24bit Sample Rate Converter

[AK4133]
Case2: ILRCK and OLRCK are not input when the PDN pin= “H”
Case 2
External clocks
(Input port)
SDTI
External clocks
(Output port)
(No Clock)
(Don’t care)
(Don’t care)
Input Clocks
Input Data
Output Clocks
Don’t care
Don’t care
Don’t care
PDN
(1)
(2)
5ms
(Internal state) Power-down LDO Up
wait ILRCK
(3)
< 20.2ms
Ratio detection
& GD
Normal
operation
Power-down
SDTO
SRCE_N
“0” data
Normal data
(4)
“0” data
Figure 17. System Reset Case2
LDO: Internal Regurator
GD: Group Delay
(1) The SDTO pin outputs “L” and the SRCE_N pin outputs “H” when the PDN pin= “L”.
(2) The internal regulator is powered up by PDN pin = “H” and wait for ILRCK and OLRCK.
(3) SRC circuit is powered up and sampling frequency ratio detection starts when ILRCK and OLRCK
are input. SDTO output starts after group delay period when the frequency ratio detection is
completed. Until then, the SDTO output is “L” and the SRCE_N pin outputs “H”. The time until SDTO
output becomes enabled after ILRCK and OLPCK input is 20.2msec (Max.).
(4) The SRCE_N pin outputs “L” when SDTO data output becomes enabled.
015015325-E-01
- 20 -
2016/06