AK4133VN Datasheet, PDF (17/28 Pages) Asahi Kasei Microsystems – 192kHz 24bit Sample Rate Converter

[AK4133]
■ System Clock for Output PORT
The output ports work in both master mode and slave mode. In master mode, the output port is operated
with OLRCK and OBICK generated from OMCLK. OLRCK and OBICK clocks are output from the
OLRCK pin and OBICK pin, respectively. In slave mode, the output port is operated by input clocks from
the OLRCK pin and the OBICK pin. The OMCLK pin is not used in slave mode. It must be connected to
DVSS.
The CM1-0 pins select master or slave mode.
Table 3. Output PORT Master/Slave Mode Control (AK4133)
Mode CM1 pin CM0 pin Master / Slave OMCLK Frequency
0
L
L
Master
1
L
H
Slave
2
H
L
Master
3
H
H
Master
Note:
* 17. The OMCLK pin must be connected to DVSS in slave mode.
256FSO
Not used. (* 17)
512FSO
128FSO
■ Audio Interface Format of the Output Port
The ODIF pin controls the audio interface mode of the output port. The data format is MSB first in 2's
complement. The data is output on a falling edge of OBICK from the SDTO pin. The audio interface
format of the output port should be changed while the PDN pin = “L”.
Mode
0
1
ODIF pin
L
H
Table 4. Output PORT Audio Interface Format
SDTO Format
OBICK (Slave)
MSB justified
I²S Compatible
 48fs or 32fs
 48fs or 32fs
OBICK (Master)
64fs
64fs
OLRCK
01 2
OBICK(64fs)
15 16 19 20 23 24
31 0 1 2
15 16 19 20 23 24
SDTO(O)
23 22
19 18
4
0
23 22
19 18
4
0
Lch Data
Rch Data
23: MSB, 0:LSB @ 24-bit
Figure 13. Mode 0 MSB Justified Timing
31 0 1
OLRCK
01 2
OBICK(64fs)
15 16 19 20 24 25
31 0 1 2
15 16 19 20 24 25
SDTO(O)
23
20 19
5
0
Lch Data
23: MSB, 0:LSB @ 24-bit
23
20 19
5
0
Rch Data
Figure 14. Mode1 I²S Compatible Timing
31 0 1
015015325-E-01
- 17 -
2016/06