AKD4128A-A Datasheet, PDF (19/52 Pages) Asahi Kasei Microsystems – AK4128A-A Evaluation Board Rev.0

[AKD4128A-A]
(2)-2. SW16(U6) setting.
Upper-side is “H” and lower-side is “L”.
SW16
No.
1
2
3
4
5
Name
DIT-OCKS1
DIT-OCKS0
DIT-DIF2
DIT-DIF1
DIT-DIF0
ON (“H”)
OFF (“L”)
Default
Master Clock Frequency Setting
H
Refer to Table 19
L
Audio Interface Format Setting
Refer to Table 20
H
L
L
Table 18. Master Clock Frequency Setting
Mode
0
1
2
3
OCKS1 pin
L
L
H
H
OCKS0 pin
MCKO1
fs (max)
L
256fs
96 kHz
H
256fs
96 kHz
L
512fs
48 kHz
H
128fs
192 kHz
Table 19. Master Clock Frequency Setting
(Default)
Mode
0
1
2
3
4
5
6
7
DIF2
pin
L
L
L
L
H
H
H
H
DIF1
pin
L
L
H
H
L
L
H
H
DIF0
pin
DAUX Format
LRCK
I/O
BICK
I/O
L 24bit, Left justified H/L O 64fs O
H 24bit, Left justified H/L O 64fs O
L 24bit, Left justified H/L O 64fs O
H 24bit, Left justified H/L O 64fs O
L 24bit, Left justified H/L O 64fs O
H 24bit, I²S Compatible L/H O
64fs
O
L 24bit, Left justified H/L I 64-128fs I
H 24bit, I²S Compatible L/H I 64-128fs I
Table 20. Audio Interface format Setting
(Default)
[KM104301]
- 19 -
2010/09