AKD4128A-A Datasheet, PDF (15/52 Pages) Asahi Kasei Microsystems – AK4128A-A Evaluation Board Rev.0

[AKD4128A-A]
(1)-2. SW3 setting
Upper-side is “H” and lower-side is “L”.
SW4
No.
1
2
3
4
5
6
7
8
Name
OBIT1
OBIT0
TDM
CM2
CM1
CM0
ODIF1
ODIF0
ON (“H”)
OFF (“L”)
Output PORT Audio Interface Format Setting 2
Refer to Table 6
TDM mode
Stereo mode
Clock Select or Mode Select pin for Output PORT
Refer to Table 7
Output PORT Audio Interface Format Setting 1
Refer to Table 5
Table4. SW4 Setting
Default
H
H
L
H
L
L
H
L
Mode
0
1
2
3
4
5
6
7
TDM
pin
L
H
ODIF1 ODIF0
pin pin
SDTO1-4 Format
L
L
LSB justified
L
H
(Reserved)
H
L
H
H
MSB justified
I²S Compatible
(Default)
L
L
L
H
(Reserved)
H
L
TDM256 mode
24bit MSB justified
H
H
TDM256 mode
24bit I²S Compatible
Table 5. Output PORT Audio Interface Format Setting 1
Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
TDM
pin
L
H
Master / Slave
setting
Slave
(CM2-0 =
“HLL” or
“HHL”)
Master
(Not CM2-0 =
“HLL”/“HHL”)
Slave
(CM2-0 =
“HLL” or
“HHL”)
OBIT1
pin
L
L
H
H
L
L
H
H
*
OBIT0
pin
L
H
L
H
L
H
L
H
*
SDTO
1-4
16bit
18bit
20bit
24bit
16bit
18bit
20bit
24bit
TDM256
mode
24bit
OLRCK
Input
Output
Input
OBICK
Input
Output
Input
OBICK Frequency
MSB
justified,
I²S
LSB
justified
≥ 32FSO
≥ 36FSO _64FSO
≥ 40FSO
≥ 48FSO
64FSO
256FSO
Master
(Not CM2-0 = *
“HLL”/“HHL”)
TDM256
*
mode Output Output
24bit
Table 6. Output PORT Audio Interface Format Setting 2
256FSO
(Default)
[KM104301]
- 15 -
2010/09