AKD4128A-A Datasheet, PDF (10/52 Pages) Asahi Kasei Microsystems – AK4128A-A Evaluation Board Rev.0

[AKD4128A-A]
(2)-1-4. Selection of SDTO1, SDTO2, SDTO3 and SDTO4.
(a) Select to SDTO1(b)Select to SDTO2 (c)Select to SDTO3 (d)Select to SDTO4
JP17
JP 17
J P17
JP17
SD T O -SEL
SD TO -SE L
SD TO-SE L
S DTO -SE L
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
(2)-2. When using all clocks are fed through the 10pin port(PORT5).
(2)-2-1.Setup TX.
As Optical connector:PORT10(OPT) and BNC connector:J5(COAX) are not used, please don’t
connect anything.
(2)-2-2. Setup the OBICK, OLRCK and SDTO.
(2)-2-2-1. When using OBICK and OLRCK of 10pin port, and SDTO of AK4128A(U1).
JP48
O BIC K
JP49
OLRCK
JP50
SDTO
JP46
DIT-OBICK SEL
DIT-Slave
DIT-M as ter
JP47
DIT-OLRCK SEL
DIT-Slave
DIT-Master
JP 18
A K41 2 8-O B ICK S EL
A K4128-Slav e
A K4128-M aster
JP19
A K4 12 8-O LR C K SE L
AK 4128-Slave
AK 4128-Master
[KM104301]
- 10 -
2010/09