AKD4128A-A Datasheet, PDF (14/52 Pages) Asahi Kasei Microsystems – AK4128A-A Evaluation Board Rev.0

[AKD4128A-A]
„ Setup the DIP SW.
(1). Setup the AK4128A(U1).
(1)-1. SW3 setting
Upper-side is “H” and lower-side is “L”.
SW3
No.
1
2
3
4
5
6
7
8
Name
IDIF2
IDIF1
IDIF0
SPB
TST1
TST2
SMSEMI
CAD0
ON (“H”)
OFF (“L”)
Audio Interface Format Setting for Input PORT
Refer to Table 3
Serial Control Mode
Parallel Control Mode
TEST Pin
Fixed to ”L”
Semi-auto Mode
Manual Mode
Chip Address 0 bit=”1” Chip Address 0 bit=”0”
Table 2. SW3 Setting
Default
L
H
L
L
L
L
L
L
Mode
0
1
2
3
4
5
6
IDIF2
pin
L
L
L
L
H
H
H
IDIF1 IDIF0
pin pin
SDTI1-4 Format
IBICK
Freq
L
L
16bit, LSB justified
≥ 32FSI
L
H
20bit, LSB justified
≥ 40FSI
H
L
24bit, MSB justified
≥ 48FSI
(Default)
H
H 24/16bit, I²S Compatible
≥ 48FSI or
32FSI
L
L
24bit, LSB justified
≥ 48FSI
L
H
H
H
Reserved
Table 3. AK4128A Audio Interface Format Setting for Input PORT
[KM104301]
- 14 -
2010/09