AKD4128A-A Datasheet, PDF (18/52 Pages) Asahi Kasei Microsystems – AK4128A-A Evaluation Board Rev.0

(2). Setup the AK4114 (U2,U3,U4,U5,U6)
(2)-1. SW6(U2), SW7(U3), SW8(U4), SW9(U5) setting.
Upper-side is “H” and lower-side is “L”.
SW6
No.
1
2
3
Name
ON (“H”)
OFF (“L”)
DIR1-OCKS1
DIR1-OCKS0
DIR1-DIF0
Master Clock Frequency Setting
Refer to Table 17
24bit, I²S Compatible 24bit, Left justified
Table 13. SW6 Setting
Default
H
L
L
SW7
No.
1
2
3
Name
ON (“H”)
OFF (“L”)
DIR2-OCKS1
DIR2-OCKS0
DIR2-DIF0
Master Clock Frequency Setting
Refer to Table 17
24bit, I²S Compatible 24bit, Left justified
Table 14. SW7 Setting
Default
H
L
L
SW8
No.
1
2
3
Name
ON (“H”)
OFF (“L”)
DIR3-OCKS1
DIR3-OCKS0
DIR3-DIF0
Master Clock Frequency Setting
Refer to Table 17
24bit, I²S Compatible 24bit, Left justified
Table 15. SW8 Setting
Default
H
L
L
SW9
No.
1
2
3
Name
ON (“H”)
OFF (“L”)
DIR4-OCKS1
DIR4-OCKS0
DIR4-DIF0
Master Clock Frequency Setting
Refer to Table 17
24bit, I²S Compatible 24bit, Left justified
Table 16. SW9 Setting
Default
H
L
L
[AKD4128A-A]
Mode
0
1
2
3
OCKS1 pin
L
L
H
H
OCKS0 pin
MCKO1
fs (max)
L
256fs
96 kHz
H
256fs
96 kHz
L
512fs
48 kHz
H
128fs
192 kHz
Table 17. Master Clock Frequency Setting
(Default)
[KM104301]
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2010/09