LU3X31T-T64 Datasheet, PDF (38/44 Pages) Agere Systems – LU3X31T-T64 Single-Port 3 10/100 Ethernet Transceiver TX

LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Clock Timing (continued)
Table 38. Receive Timing
Symbol
t1
t2
t3
t4
Description
Min
Receive Frame to Sampled Edge of RXDV
—
(100 Mbits/s)
Receive Frame to Sampled Edge of RXDV
—
(10 Mbits/s)
Receive Frame to CRS High (100 Mbits/s)
—
Receive Frame to CRS High (10 Mbits/s)
—
End of Receive Frame to Sampled Edge of
—
RXDV (100 Mbits/s)
End Receive Frame to Sampled Edge of RXDV
—
(10 Mbits/s)
End of Receive Frame to CRS Low (100 Mbits/s) 13
End of Receive Frame to CRS Low (10 Mbits/s)
—
Preliminary Data Sheet
July 2000
Max
Unit
15
bits
22
bits
13
bits
5
bits
12
bits
4
bits
24
bits
4.5
bits
RXCLK
RXDV
CRS
TPRX
t1
t2
DATA
t3
t4
Figure 12. Receive Timing
5-6790(F)
38
Lucent Technologies Inc.