LU3X31T-T64 Datasheet, PDF (29/44 Pages) Agere Systems – LU3X31T-T64 Single-Port 3 10/100 Ethernet Transceiver TX

Preliminary Data Sheet
July 2000
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
MII Registers (continued)
Table 23. PHY Address Register (Register 19h)
Bit(s)
15:11
10:5
4:0
Name
Reserved
User Seed
PHY Address
Description
Reserved.
User-modifiable seed data. When the
load seed bit (bit 4 of register 18h) is set,
bits 15 through 5 of this register are
loaded into the 100Base-X scrambler.
These 5 bits store the part address used
by the serial management interface. PHY
address of 0 has the special function of
isolating the part from the MII. These bits
are initialized to the logic levels of
PHY[4:0] pins at powerup or reset.
R/W
RO
R/W
R/W
Table 24. Config 10 Register (Register 1Ah)
Bit(s)
Name
Description
R/W
15
Reserved
Reserved.
RO
14
Force 10 Mbits/s Good 1Force 10 Mbits/s good link.
R/W
Link
0Normal operation.
13
Reserved
Reserved.
RO
12
SQE Disable
1Signal quality error test disabled.
R/W
0Normal operation.
11
Low Squelch Select 1Low squelch level selected.
R/W
0Normal squelch level selected.
10
Jabber Disable
1Jabber function disabled.
R/W
0Normal operation.
9:7
Reserved
Reserved.
RO
6
Powerdown Mode
1—Powers down the LU3X31T-T64 com- R/W
pletely. The part comes out of this
mode after a reset is asserted and
deasserted.
0—Normal operation.
5:4
Reserved
Reserved.
RO
3
Autopolarity Disable 1—Disable autopolarity function.
R/W
0—Enable autopolarity function.
2:0
Reserved
Reserved.
RO
Default
0h
21h
Pin
Default
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
Lucent Technologies Inc.
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