LU3X31T-T64 Datasheet, PDF (1/44 Pages) Agere Systems – LU3X31T-T64 Single-Port 3 10/100 Ethernet Transceiver TX

Preliminary Data Sheet
July 2000
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Overview
The LU3X31T-T64 is a fully integrated
10/100 Mbits/s physical layer device with an inte-
grated transceiver. It is provided in a 64-pin TQFP
package with low-power operation and powerdown
modes. Typical applications for this part are CardBus
and PCMCIA Ethernet products. Operating at 3.3 V,
the LU3X31T-T64 is a powerful device for the forward
migration of legacy 10 Mbits/s products and noncom-
pliant (does not have autonegotiation) 100 Mbits/s
devices. The LU3X31T-T64 was designed from the
beginning to conform fully with all pertinent specifica-
tions, from the ISO^*/IEC 11801 and EIA^†/TIA 568
cabling guidelines to ANSI^‡ X3.263 TP-PMD to
IEEE ^§ 802.3 Ethernet specifications.
Features
s Single-chip integrated physical layer and trans-
ceiver for 10Base-T and/or 100Base-T functions
s IEEE 802.3 compatible 10Base-T and 100Base-T
physical layer interface and ANSI X3.263 TP-PMD
compatible transceiver
s Built-in analog 10 Mbits/s receive filter, eliminating
the need for external filters
s Built-in 10 Mbits/s transmit filter
s 10 Mbits/s PLL exceeding tolerances for both pre-
amble and data jitter
s 100 Mbits/s PLL, combined with the digital adap-
tive equalizer, robustly handles variations in rise-
fall time, excessive attenuation due to channel
loss, duty-cycle distortion, crosstalk, and baseline
wander
s Transmit rise-fall time can be manipulated to pro-
vide lower emissions, amplitude fully compatible
for proper interoperability
s Programmable scrambler seed for better FCC
compliancy
s IEEE 802.3u Clause 28 compliant autonegotiation
for full 10 Mbits/s and 100 Mbits/s control
s Fully configurable via pins and management
accesses
s Extended management support with interrupt
capabilities
s PHY MIB support
s Symbol mode option
s Low-power operation: <150 mA max
s Low autonegotiation power: <30 mA
s Very low powerdown mode: <5 mA
s 64-pin TQFP package (10 mm x 10 mm x 1.4 mm)
* ISO is a registered trademark of The International Organization
for Standardization.
† EIA is a registered trademark of The Electronic Industries Asso-
ciation.
‡ ANSI is a registered trademark of The American National Stan-
dards Institute, Inc.
§ IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.