LU3X31T-T64 Datasheet, PDF (28/44 Pages) Agere Systems – LU3X31T-T64 Single-Port 3 10/100 Ethernet Transceiver TX

LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Preliminary Data Sheet
July 2000
MII Registers (continued)
Table 21. PHY Control/Status Register (Register 17h) (continued)
Bit(s)
Name
Description
R/W Default
0 LED Pulse Stretching Disable 1LED pulse stretching disabled.
R/W
0
0LED pulse stretching enabled.
When pulse stretching is enabled, all LED
outputs are stretched to 48 ms—72 ms.
Table 22. Config 100 Register (Register 18h)
Bit(s)
15
14
13
12
11:10
9
8:6
5
4
3
2:0
Name
BPSCR
BP4B5B
Reserved
BPALIGN
Reserved
Force Good Link 100
Reserved
Accept Halt
Load Seed
Burst Mode
Reserved
Description
1Disable scrambler/descrambler.
0Enable scrambler/descrambler.
This bit is initialized to the logic level of
BPSCR pin (pin 41) at powerup or reset.
1Disable 4B/5B encoder/decoder.
0Enable 4B/5B encoder/decoder.
This bit is initialized to the logic level of
BP4B5B pin (pin 42) at powerup or reset.
Reserved.
1Pass unaligned data to MII.
0Pass aligned data to MII.
This bit is initialized to the logic level of
BPALIGN pin (pin 44) at powerup or reset.
Reserved.
1Force good link in 100 Mbits/s mode.
0Normal operation.
Reserved.
1Passes HALT symbols to the MII.
0Normal operation.
1Loads the scrambler seed.
0Normal operation.
Setting this bit loads the user seed stored
in register 19h into the 100Base-X scram-
bler. The content of this bit returns to 0
after the loading process is completed and
no transmit is active.
1Burst mode.
0Normal operation.
Setting this bit expands the 722 µs scram-
bler time-out period to 2,000 µs.
Reserved.
R/W
R/W
R/W
RO
R/W
RO
R/W
RO
R/W
R/W, SC
R/W
RO
Default
Pin
Pin
0h
Pin
0h
0h
0h
0h
0h
0h
0h
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