LU3X31T-T64 Datasheet, PDF (15/44 Pages) Agere Systems – LU3X31T-T64 Single-Port 3 10/100 Ethernet Transceiver TX

Preliminary Data Sheet
July 2000
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Functional Description (continued)
Upon detection of sufficient IDLE symbols within the
722 µs period, the hold timer will reset and begin a new
countdown. This monitoring operation will continue
indefinitely given a properly operating network connec-
tion with good signal integrity. If the link state monitor
does not recognize sufficient unscrambled IDLE sym-
bols within the 722 µs period, the entire descrambler
will be forced out of the current state of synchronization
and reset in order to reacquire synchronization. Regis-
ter 18h, bit 3, can be used to extend the timer to
2000 µs.
Symbol Alignment. The symbol alignment circuit in
the LU3X31T-T64 determines code word alignment by
recognizing the /J/K delimiter pair. This circuit operates
on unaligned 5-bit data from the descrambler and is
capable of finding /J/K at any of the five possible start-
ing positions within the descrambled data quints. Once
the /J/K symbol pair (11000 10001) is detected, subse-
quent data is aligned on a fixed boundary.
Symbol Decoding. The symbol decoder functions as
a look-up table that translates incoming 5B symbols
into 4B nibbles. The symbol decoder first detects the
/J/K symbol pair preceded by IDLE symbols and
replaces the symbol with MAC preamble. All subse-
quent 5B symbols are converted to the corresponding
4B nibbles for the duration of the entire packet. This
conversion ceases upon the detection of the /T/R sym-
bol pair denoting the end of stream delimiter (ESD).
The translated data is presented on the RXD[3:0] sig-
nal lines with RXD[0] representing the least significant
bit of the translated nibble.
Valid Data Signal. The valid data signal (RXDV) indi-
cates that recovered and decoded nibbles are being
presented on the RXD[3:0] outputs synchronous to
RXCLK. RXDV is asserted when the first nibble of
translated /J/K is ready for transfer over the media
independent interface (MII). It remains active until
either the /T/R delimiter is recognized, link test indi-
cates failure, or no signal is detected. On any of these
conditions, RXDV is deasserted.
Receiver Errors. The RXER signal is used to commu-
nicate receiver error conditions. While the receiver is in
a state of holding RXDV asserted, the RXER will be
asserted for each code word that does not map to a
valid code-group.
100Base-X Link Monitor
The 100Base-X link monitor function allows the
receiver to ensure that reliable data is being received.
Without reliable data reception, the link monitor will halt
both transmit and receive operations until such time
that a valid link is detected.
The LU3X31T-T64 performs the link integrity test as
outlined in IEEE 100Base-X (Clause 24) link monitor
state diagram. The link status is multiplexed with the
10 Mbits/s link status to form the reportable link status
bit in serial management register 1. This status also
drives the LNKLED pin.
When persistent signal energy is detected on the net-
work, the logic moves into a Link-Ready state, after
approximately 500 µs, and waits for an enable from the
autonegotiation module. When received, the link-up
state is entered, and the transmit and receive logic
blocks become active. Should autonegotiation be dis-
abled, the link integrity logic moves immediately to the
link-up state after entering the link-ready state.
Carrier Sense. Carrier sense (CRS) for 100 Mbits/s
operation is asserted upon the detection of two non-
contiguous zeros occurring within any 10-bit boundary
of the receive data stream.
The carrier sense function is independent of symbol
alignment. For 100 Mbits/s half-duplex operation, CRS
is asserted during either packet transmission or recep-
tion. For 100 Mbits/s full-duplex operation, CRS is
asserted only during packet reception. When the IDLE
symbol pair is detected in the receive data stream,
CRS is deasserted.
Bad SSD Detection. A bad start of stream delimiter
(Bad SSD) is an error condition that occurs in the
100Base-X receiver if carrier is detected (CRS
asserted) and a valid /J/K set of code groups (SSD) is
not received.
If this condition is detected, then the LU3X31T-T64 will
assert RXER and present RXD[3:0] = 1110 to the MII
for the cycles that correspond to received 5B code-
groups until at least two IDLE code groups are
detected. Once at least two IDLE code groups are
detected, RXER and CRS become deasserted.
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