LU3X31T-T64 Datasheet, PDF (22/44 Pages) Agere Systems – LU3X31T-T64 Single-Port 3 10/100 Ethernet Transceiver TX

LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Preliminary Data Sheet
July 2000
MII Registers (continued)
Table 13. Control Register (Register 0h) (continued)
Bit(s)
11
10
9
8
7
6:0
Name
Powerdown
Isolate
Restart Autonegotiation
Duplex Mode
Collision Test
Reserved
Description
1Powerdown.
0Normal operation.
Setting this bit puts the LU3X31T-T64 into
powerdown mode. During the powerdown
mode, TPTX± and all LED outputs are 3-
stated, and the MII interface is isolated.
RSTZ is used to clear this bit.
1Isolate PHY from MII.
0Normal operation.
Setting this control bit isolates the
LU3X31T-T64 from the MII, with the excep-
tion of the serial management interface.
When this bit is asserted, the LU3X31T-T64
does not respond to TXD[3:0], TXEN, and
TXER inputs, and it presents a high imped-
ance on its TXCLK, RXCLK, RXDV, RXER,
RXD[3:0], COL, and CRS outputs. This bit is
initialized to 0 unless the configuration pins
for the PHY address are set to 00000h during
powerup or reset.
1Restart autonegotiation process.
0Normal operation.
Setting this bit while autonegotiation is
enabled forces a new autonegotiation pro-
cess to start. This bit is self-clearing and
returns to 0 after the autonegotiation process
is completed.
1Full-duplex mode.
0Half-duplex mode.
If autonegotiation is disabled, this bit deter-
mines the duplex mode for the link.
At powerup or reset, this bit is set to 1 if the
AUTONEN pin (pin 4) detects a logic 0 and
either 100FDEN (pin 2) or 10FDEN pin (pin
17) detects a logic 1.
1Enable COL signal test.
0Disable COL signal test.
When set, this bit will cause the COL signal
to be asserted in response to the assertion of
TXEN.
Not used.
R/W
R/W
R/W
R/W, SC
R/W
R/W
RO
Default
0h
Pin
0h
Pin
0h
0h
22
Lucent Technologies Inc.