LU6612 Datasheet, PDF (28/36 Pages) Agere Systems – LU6612 FASTCAT TM Single-FET for 10Base-T/100Base-TX

LU6612
FASTCAT Single-FET for 10Base-T/100Base-TX
Timing Characteristics (Preliminary) (continued)
Table 27. Serial 10 Mbits/s Timing for RX/RY, CRS, and RX_CLK
Name
t15
t16
t17
t18
Parameter
RX/RY Activity to CRS Assertion
RX/RY Activity to RX_CLK Valid
IDL to CRS Deassertion
Dead Signal to CRS Deassertion
Data Sheet
July 2000
Min
Max Unit
40
500
ns
800
2300 ns
200
550
ns
400
1000 ns
RX/RY
(RECEIVE—START OF PACKET)
(RECEIVE—DEAD SIGNAL)
(NOT IDL)
(RECEIVE—END OF PACKET)
IDL
CRS
RX_CLK
t15
t17
t18
t16
Figure 10. Serial 10 Mbits/s Timing for RX/RY, CRS, and RX_CLK
5-5293(F).mr1
Table 28. Serial 10 Mbits/s Timing for TX_EN, TX/TY, CRS, and RX_CLK
Name
t19
t20
t21
t22
t23
Parameter
TX_EN Asserted to Transmit Pair Activity
TX_EN Asserted to CRS Asserted Due to Internal Loopback
TX_EN Asserted to RX_CLK Valid Due to Internal Loopback
TX_EN Deasserted to IDL Transmission
IDL Pulse Width
Min
50
5
1000
50
250
Max Unit
400 ns
1900 ns
1700 ns
300 ns
350 ns
TX_EN
(TRANSMIT—START OF PACKET)
(TRANSMIT—END OF PACKET)
TX/TY
t19
CRS
IDL
t22
t23
t20
RX_CLK
t21
Figure 11. Serial 10 Mbits/s Timing for TX_EN, TX/TY, CRS, and RX_CLK
5-5293(F).nr1
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Lucent Technologies Inc.