LU6612 Datasheet, PDF (12/36 Pages) Agere Systems – LU6612 FASTCAT TM Single-FET for 10Base-T/100Base-TX

LU6612
FASTCAT Single-FET for 10Base-T/100Base-TX
Data Sheet
July 2000
Pin Information (continued)
Table 5. Miscellaneous Pins (20) (continued)
Signal Type* Pin
Description
SPEED- I/O
LED/
PHYAD[2]
56 Speed LED. This pin indicates the operating speed of LU6612:
s LED is active when in 100 Mbits/s operation.
s LED is not active when in 10 Mbits/s operation.
FUDU- I/O
PLED/
PHYAD[3]
At powerup/reset, this pin is sampled as input and to set the PHYAD[2] bit. If pulled
high through a resistor, this pin will set PHYAD[2] to a high or if pulled low through a
resistor, will set PHYAD[2] to a zero. When this pin is pulled high, the LED output will
be active-low, when pulled low, the LED output will be active-high.
55 Full-Duplex LED. This pin indicates the operating mode of LU6612 and is only valid
when link is up:
s LED is active when in full-duplex mode of operation.
s LED is not active when in half-duplex mode of operation.
At powerup/reset, this pin is sampled as an input to set the PHYAD[3] bit. If pulled
high through a resistor, this pin will set PHYAD[3] to a high or if pulled low through a
resistor, will set PHYAD[3] to a zero. When this pin is pulled high, the LED output will
be active-low, when pulled low, the LED output will be active-high.
PHYAD[4] I↑
17 PHYAD[4]. At powerup/reset, this pin is sampled as an input to set the PHYAD[4] bit.
If pulled high through a resistor, this pin will set PHYAD[4] to a high or if pulled low
through a resistor, will set PHYAD[4] to a zero. This pin has an internal 100 kΩ pull-
up resistor.
MODE[2:0] I↑ 52:50 Mode Selection. These pins carry encoded signals that are latched into the LU6612
upon powerup/reset and define specific modes of operation: half/full duplex, autone-
gotiation enabled/disabled, and transceiver isolation. Refer to Table 20 for the various
modes and how various registers are affected. Pins [52:50] have internal 100 kΩ pull-
ups. If left floating, LU6612 will default to all capable, autonegotiation enabled mode.
TEST[0] I↑ 15 Test Enable Pin for Factory Testing. This pin has an internal 100 kΩ pull-down
resistor. The pin can be either left floating or tied down.
TEST[2:1] I↓ 19, Test Enable Pin for Factory Testing. These two pins have internal 50 kΩ pull-down
16 resistors. These pins can either be left floating or tied low.
CLKREF
I
12 Clock Reference. Connect this pin to a 1 nF ± 10% capacitor to ground.
RESET
I
27 Full Chip Reset (Active-Low). Reset is an active-low signal. Reset must be
asserted low for at least five LSCLK cycles. The LU6612 will come out of reset after
400 µs. LSCLK1 must remain running during reset.
BGREF[1:0] I 57:58 Band-Gap Reference. Connect these pins to a 24.9 kΩ ± 1% resistor to ground. The
parasitic load capacitance should be less than 15 pF.
ISET_100 I
2 Current Set 100 Mbits/s. An external reference resistor (24.9 kΩ) is placed from this
pin to ground to set the 100 Mbits/s TP driver transmit output level.
ISET_10
I
24 Current Set 10 Mbits/s. An external reference resistor (22.1 kΩ) is placed from this
pin to ground to set the 10 Mbits/s TP driver transmit output level.
PCSEN
I↑ 18 PCS Enable (Active-Low). When this pin is active-low, the encoded 5-bit symbols
appear on RXD[4:0] and TXD[4:0]. When this pin high, 4-bit data appears on
RXD[3:0] and TXD[3:0]. When PCSEN is low, LU6612 bypasses the 4B5B encoder/
decoder, the align function, the scrambler/descrambler, and does not detect and gen-
erate J/K and R/T code groups at the start or end of frame. This pin has an internal
100 kΩ pull-up.
* ↑ indicates there is an internal pull-up; ↓ indicates there is an internal pull-down.
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