CT1611 Datasheet, PDF (9/24 Pages) Aeroflex Circuit Technology – DMA Controller with Buffer Memory,MIL-STD-1750A Compatible

ADDRESS
(From DMA Controller)
DMA STRBD
(From DMA Controller)
DMA DATA ACK
(From UP System)
DATA
(From UP System)
DMA ACK
(From UP System)
DMA REQ
(From DMA Controller)
TRISTATE
50ns MIN
500ns
FIRST
666ns
50ns MIN
Extended 1 Cycle
333ns MIN
120ns MAX or Cycle Extended
250ns MIN
220ns MAX
TRISTATE
Note 2
VALID
330ns MIN
0ns MIN / 18µs MAX
Notes:
1. R / W from DMA Controller = Logic "1".
2. DATA will be valid within 220ns of STRBD or VALID with DMA DATA ACK.
DMA READ OPERATION
LAST
TRISTATE
TRISTATE
100ns MIN
R/W
(From DMA Controller)
ADDRESS / DATA
(From DMA Controller)
DMA STRBD
(From DMA Controller)
DMA DATA ACK
(From UP System)
DMA ACK
(From UP System)
DMA REQ
(From DMA Controller)
VALID MSG RCV’D
(Interrupt from DMA Controller)
Tristate pulled HIGH
TRISTATE
50ns MIN
500ns
FIRST
666ns
500ns
50ns MIN
Extended 1 Cycle
250ns MIN
65ns MAX or Cycle Extended
250ns MIN
330ns MAX
0ns MIN /27µs MAX
Notes:
1. If a DMA DATA ACK is not implemented in system, DMA DATA ACK should be
either connected to DMA STRBD (preferred) or tied LOW.
2. Preferred method for resetting DMA DATA ACK HIGH is with trailing edge of DMA STRBD.
DMA WRITE OPERATION
Tristate pulled HIGH
LAST
TRISTATE
100ns MAX
500ns TYP
SCDCT1611 Rev A
9