CT1611 Datasheet, PDF (2/24 Pages) Aeroflex Circuit Technology – DMA Controller with Buffer Memory,MIL-STD-1750A Compatible

been serviced. Use of the interrupts is optional. The interrupt signals
are the same for bus control operation although different in meaning.
Interrupts for received or transmitted data messages are generated
after the DMA transfers have been completed.
The Busy, Service Request, and Subsystem Error bits for the status
word are contained in a dedicated register accessible via I/O. The
Busy bit is set high at power-up as well as via a subsystem reset.
BC OPERATION
The CT1611 is programmable into Bus Controller operation via I/O
from the subsystem. Under Bus Controller mode, there are two
command word registers, a received mode data register, two returned
status word registers, an error latch and a transaction word register.
The first command register is used for all 1553 bus transfers. The
second command register is for the second command word used in
RT to RT transfers or for the associated mode data required for
certain mode codes.
The CT1611 provides full validity checking for all 1553 transfers
and alerts the subsystem, via interrupts, as to whether the transfer
was valid or not. The two status word registers are preset high at the
initiation of a transfer and may be read at completion. The second
status word is provided for RT to RT transfers. The error latch may
be used to determine the nature of a failure should a transfer be
unsuccessful.
The transaction word register is used to define the type of transfer to
be performed, to which bus the transfer is to be made, and to define
which bits (when set) in the returned status word constitute an invalid
transfer.
A polling operation has also been included that enables the CT1611
to automatically load the command words and transaction words
from main memory via DMA. This function allows a
preprogrammed polling sequence of the remote terminals to be
implemented with a minimum of subsystem intervention.
SCDCT1611 Rev A
2