CT1611 Datasheet, PDF (1/24 Pages) Aeroflex Circuit Technology – DMA Controller with Buffer Memory,MIL-STD-1750A Compatible

Standard Products
CT1611 Microprocessor Interface
DMA Controller with Buffer Memory,
MIL-STD-1750A Compatible
www.aeroflex.com
September 16, 2003
FEATURES
‰ Full Bus Control and RTU Operation
‰ Low Software Overhead
‰ Complete BI-Directional Message Buffer
‰ Memory-Mapped DMA Message Transfers
‰ Simple Programmable Polling Operation in Bus Controller Mode
‰ Pin Programmable for both 8 and 16 Bit Microprocessors
‰ Monolithic construction using linear ASICs
‰ Processed and screened to MIL-STD-883 specs
‰ Aeroflex is a Class H & K MIL-PRF-38534 Manufacturer
‰ MIL-PRF-38534 Compliant Devices Available
GENERAL
The CT1611 provides a complete Bus Controller and Remote
Terminal interface between the MIL-STD-1553B chip set (CT1561,
CT1602, CT1610, etc.) and most microprocessor-based systems
(F9450A, 68000, 8086, VME bus, Multibus, etc.). The unit is
constructed totally with CMOS technology and includes a custom
CMOS chip, two HC CMOS FIFO's and HCT CMOS buffers. Thus
the interface has extremly low power requirements.
The CT1611 interface permits the use of all 15 mode codes and all
types of data transfers as specified in MIL-STD-1553B in both Bus
Controller and Remote Terminal operating modes. A Remote Terminal
is capable of switching to a Bus Controller when requested via the
Dynamic Bus Control mode code.
DATA TRANSFERS
Data transfers in both Bus Controller and Remote Terminal operation
are performed via a DMA burst. This powerful feature insures that the
host microprocessor system will never be held up more than 16.5 usec
when transferring 32 data words into or out of the interface. It also
insures that only good and complete messages will be transferred to
the host's memory. Operation of the DMA is as follows: When data is
received from the 1553 cable via the chip set, it is loaded into an
internal FIFO at the 20 µsec/word 1553 rate. Once the complete
message has been received and has passed all validity tests, the
CT1611 issues the signal DMA REQ to the subsystem. (This signal
corresponds to a HOLD request in many systems.) The host
microprocessor then acknowledges and grants this request by issuing
the signal DMA ACK. The CT1611 then becomes the bus master of
the subsystem and transfers all the data on a memory-mapped basis.
When the transfer is complete, the CT1611 removes its DMA REQ
and returns control of the microprocessor bus to the microprocessor.
When data is to be transmitted on the 1553 cable, a similar DMA takes
place. Data is preloaded into the FIFO via a single DMA burst and
then transmitted.
As a failsafe, an internal timeout is provided to insure that the CT1611
can never control the microprocessor bus longer than 80 µsec. In
addition, a hard-wired Master Reset input signal is provided that will
place all output signals in a tri-state condition. Therefore, in the
unlikely condition of a failure in the CT1611, the host microprocessor
system can never be brought down or placed in a non-recoverable
state.
SCDCT1611 Rev A
A built-in test function has been included to exercise the DMA
operation and verify the message data path. This function is initiated
by an I/O command from the subsystem.
I/O CONTROL
The CT1611 can be addressed, written to, read from, and programmed
much like any peripheral device located on a microprocessor bus. The
address lines and a device select input signal allow the subsystem to
read or write to the CT1611 as if it were memory. In view of the fact
that microprocessors are becoming very fast, two types of handshake
signals were incorporated into the CT1611, either of which may be
used to permit asynchronous read and write operations. Handshaking
directly with the 9450A, 8085, 8086 and the 6802 is the active high
Ready signal. Handshaking directly with the 68000 or VME and
Multibus busses is the active low Acknowledge signal.
INTERFACING
To accomodate both 8 and 16 bit microprocessor data busses, the
CT1611 data path is pin programmable for either operation. When
operating in 8 bit mode, data is DMA'd in 8 bit bytes and therefore
requires twice the time to be transferred.
Bus control signals are pin programmable for either individual read
and write strobes or a common read/write signal and data strobe.
Individual read and write strobes are used with the Intel 8085, 8086
and Multibus. A common read/write signal and data strobe are used
with the 9450A, 6802, 68000 and VME bus. Two separate pins are
provided for input and output data strobes. These signals may be
connected or kept separate to insure that 1553 data can never be
written into a protected area of memory.
RTU OPERATION
The CT1611 is powered-up and reset as a Remote Terminal. In
addition, in Bus Controller mode, it can be changed into a Remote
Terminal via an I/O command.
In Remote Terminal mode, the CT1611 uses dedicated registers for the
received command word, the sync data word, and the vector word. The
command word register contains a second tier so that receive
command words are double buffered. This feature maximizes the
allowable I/O access time.
Four interrupts are provided to alert the subsystem that a valid
message has been received or transmitted or that a mode command has