ADP1853 Datasheet, PDF (9/28 Pages) Analog Devices – Synchronous, Step-Down DC-to-DC Controller

Data Sheet
ADP1853
Pin No. Mnemonic
17
PGOOD
18
RAMP
19
FREQ
20
TRK
EPAD
Description
Power Good. The open-drain power good indicator logic output with an internal 12.5 kΩ resistor is connected
between PGOOD and VCCO. PGOOD is pulled to ground when the output is outside the regulation window. An
external pull-up resistor is not required. If the controller is configured as a slave in the interleaved dual-phase
application by tying the FB pin high to VCCO, the pulse skip mode is enabled by driving the PGOOD pin low
externally in cases when the master is in pulse skip mode at light loads. Otherwise, if the master is configured to
forced PWM operation, PGOOD of the slave controller must be connected to the PGOOD of the master.
Programmable Current Setting for Slope Compensation. Connect a resistor from RAMP to V_IN. The voltage at RAMP
is 0.2 V during operation. This pin is high impedance when the channel is disabled.
Internal Oscillator Frequency, f_OSC. Sets the desired operating frequency between 200 kHz and 1.5 MHz with one
resistor between FREQ and AGND. Connect FREQ to AGND for a preprogrammed 300 kHz or tie FREQ to VCCO for
600 kHz operating frequency.
Tracking Input. Connect TRK to VCCO if tracking is not used.
Exposed Pad. Connect the bottom of the exposed pad to the system AGND plane.
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