ADP1853 Datasheet, PDF (12/28 Pages) Analog Devices – Synchronous, Step-Down DC-to-DC Controller

ADP1853
THEORY OF OPERATION
The ADP1853 is a fixed frequency, step-down, synchronous
switching controller with integrated drivers and bootstrapping
for external N-channel power MOSFETs. The current mode
control loop can also be configured into the voltage mode. The
controller can be set to operate in pulse skip mode for power
saving at a light load or in forced PWM. The ADP1853 includes
programmable soft start, output overvoltage protection, pro-
grammable current limit, power good, and tracking functions.
The controller can operate at a switching frequency between
200 kHz and 1.5 MHz that is programmed with a resistor or
synchronized to an external clock. It also has the internal clock
out signal that can be used to synchronize other devices.
CONTROL ARCHITECTURE
The ADP1853 is based on a fixed frequency, emulated peak
current mode, PWM control architecture. The inductor current
is sensed by the voltage drop measured across the external low-
side MOSFET, R_DSON, or across the sense resistor placed in series
between the low-side MOSFET source and the power ground.
The current is sensed during the off period of the switching
cycle and is conditioned with the internal current sense
amplifier. The gain of the current sense amplifier is pro-
grammable to 3 V/V, 6 V/V, or 12 V/V during the controller
power-up initialization before the device starts switching. A
47 kΩ resistor between DL and PGND programs the gain of
3 V/V; a 22 kΩ resistor sets a gain of 6 V/V. Without a resistor,
the gain is programmed to 12 V/V. The output signal of the
current sense amplifier is held, added to the emulated current
ramp in the next switching cycle during the DH on time, and
fed into the PWM comparator, as shown in Figure 16. This
signal is compared with the COMP signal from the error
amplifier and resets the flip-flop, which generates the PWM
pulse. If voltage mode control is selected by placing a 100 kΩ
resistor between DL and PGND, the emulated ramp is fed to the
PWM comparator without adding the current sense signal.
V_IN
V_IN
I_RAMP
R_RAMP
OSC
SQ
FF
RQ
TO
DRIVERS
A_R
C_R
V_CS
A_CS
FROM
ERROR AMP
CS
PGND
Figure 16. Simplified Control Architecture
Data Sheet
As shown in Figure 16, the emulated current ramp is generated
inside the IC, but offers programmability through the RAMP
pin. Selecting an appropriate value resistor between V_IN to the
RAMP pin programs a desired slope compensation value, and at
the same time, provides a V_IN feed forward feature. Control
logic enforces antishoot-through operation to limit cross
conduction of the internal drivers and external MOSFETs.
OSCILLATOR FREQUENCY
The internal oscillator frequency, which ranges from 200 kHz
to 1.5 MHz, is set by an external resistor, R_FREQ, at the FREQ
pin. Some popular f_OSC values are shown in Table 4, and a
graphical relationship is shown in Figure 17. For instance, a 78.7
kΩ resistor sets the oscillator frequency to 800 kHz.
Furthermore, connecting FREQ to AGND or FREQ to VCCO
sets the oscillator frequency to 300 kHz or 600 kHz,
respectively. For other frequencies that are not listed in Table 4,
the values of R_FREQ
and f_OSC can be obtained from Figure 17, or use the following
empirical formula to calculate these values:
R_FREQ (kΩ) = 96,568 × f_OSC (kHz)^−1.065
Table 4. Setting the Oscillator Frequency
R_FREQ
f_OSC (Typical)
332 kΩ
200 kHz
78.7 kΩ
800 kHz
60.4 kΩ
1000 kHz
51 kΩ
1200 kHz
40.2 kΩ
1500 kHz
FREQ to AGND
300 kHz
FREQ to VCCO
600 kHz
410
360
310
260
210
160
110
60
10
100
R_FREQ (kΩ) = 96,568 f_OSC (kHz)^–1.065
400
700
1000
1300
1600
1900
f_OSC (kHz)
Figure 17. R_FREQ vs. f_OSC
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