ADP1853 Datasheet, PDF (23/28 Pages) Analog Devices – Synchronous, Step-Down DC-to-DC Controller

Data Sheet
Use the larger value of C_I from Equation 14 or Equation 15.
Because of the finite output current drive of the error amplifier,
C_I needs to be less than 10 nF. If it is larger than 10 nF, choose a
larger R_TOP and recalculate R_Z and C_I until C_I is less than 10 nF.
Next, choose the high frequency pole, f_P1, to be ½ of f_SW.
f _P1
=
1
2
f _SW
(16)
Because C_HF << C_I,
f _P1
=
1
2πR_ZC _HF
(17)
Combine Equation 16 and Equation 17, and solve for C_HF,
C _HF
=
1
πf _SW R_Z
(18)
For maximally precise compensation solutions, use the
ADIsimPower design tool.
SWITCHING NOISE AND OVERSHOOT REDUCTION
To reduce voltage ringing and noise, it is recommended to add
an RC snubber between SW and PGND for high current
applications, as illustrated in Figure 30.
In most applications, R_SNUB is typically 2 Ω to 4 Ω, and C_SNUB is
typically 1.2 nF to 3 nF.
The size of the RC snubber components must be chosen
correctly to handle the power dissipation. The power dissipated
in R_SNUB is
P_SNUB = V_IN ² × C _SNUB × f _SW
In most applications, a component size of 0805 for R_SNUB is
sufficient. The RC snubber does not reduce the voltage over-
shoot. A resistor, shown as R_RISE in Figure 30, at the BST pin
helps to reduce overshoot and is generally between 2 Ω and
4 Ω. Adding a resistor in series, typically between 2 Ω and
4 Ω, with the gate driver also helps to reduce overshoot. If a
gate resistor is added, then R_RISE is not needed.
ADP1853
R_RISE
BST
DH
SW
DL
PGND
V_IN
M1
L
M2 ^RSNUB
C_SNUB
V_OUT
C_OUT
Figure 30. Application Circuit with a Snubber
ADP1853
VOLTAGE TRACKING
The ADP1853 includes a tracking feature that tracks a master
voltage. In all tracking configurations, the output can be set as
low as 0.6 V for a given operating condition. The soft start time
setting of the master voltage should be longer than the soft start
of the slave voltage. This forces the rise time of the master
voltage to be imposed on the slave voltage. If the soft start
setting of the slave voltage is longer, the slave comes up more
slowly, and the tracking relationship is not seen at the output.
Two tracking configurations are possible with the ADP1853:
coincident and ratiometric tracking.
Coincident Tracking
The most common application is coincident tracking, used
in core vs. I/O voltage sequencing and similar applications.
Coincident tracking forces the ramp rate of the output voltage
to be the same for the master and slave until the slave output
reaches its regulation. Connect the slave TRK input to a resistor
divider from the master voltage that is the same as the divider
used on the slave FB pin. This forces the slave voltage to be the
same as the master voltage. For coincident tracking, use R_TRKT =
R_TOP and R_TRKB = R_BOT, as shown in Figure 32.
MASTER VOLTAGE
SLAVE VOLTAGE
TIME
Figure 31. Coincident Tracking
3.3V
V_{OUT_MASTER}
1.8V
V_{OUT_SLAVE}
R_TRKT
20kΩ
1.1V
R_TRKB
10kΩ
ADP1853
TRK FB
R_TOP
20kΩ
R_BOT
10kΩ
C_SS
SS
20nF
Figure 32. Example of a Coincident Tracking Circuit
The ratio of the slave output voltage to the master voltage is a
function of the two dividers.
V_{OUT _SLAVE}
=
^{1 +}
R_TOP
R_BOT

V_{OUT _ MASTER}
^{1 +}
R_TRKT
R_TRKB

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