EVAL-ADF7021DBZ5 Datasheet, PDF (59/64 Pages) Analog Devices – High Performance Narrow-Band Transceiver IC

Data Sheet
REGISTER 13—3FSK/4FSK DEMOD REGISTER
Refer to the Receiver Setup section for information about programming these settings.
3FSK_PREAMBLE_
TIME_VALIDATE
3FSK_CDR_ THRESHOLD
3FSK/4FSK_
SLICER_THRESHOLD
CONTROL
BITS
ADF7021
VT7 ...
0
...
0
...
0
...
0
...
.
...
.
...
1
...
3FSK CDR
VT3 VT2 VT1 THRESHOLD
0 0 0 OFF
0011
0102
0113
.
.
.
.
.
.
.
.
1 1 1 127
3FSK VITERBI
VD1 _DETECTOR
0 DISABLED
1 ENABLED
PHASE
PC1 _CORRECTION
0 DISABLED
1 ENABLED
VITERBI PATH
VM2 VM1 MEMORY
0 0 4 BITS
0 1 6 BITS
1 0 8 BITS
1 1 32 BITS
ST7 ...
0
...
0
...
0
...
0
...
.
...
.
...
1
...
SLICER
ST3 ST2 ST1 THRESHOLD
0 0 0 OFF
0011
0102
0113
.
.
.
.
.
.
.
.
1 1 1 127
3FSK PREMABLE
PTV4 PTV3 PTV2 PTV1 TIME VALIDATE
0 0 00 0
00011
00102
00113
.
.
.
.
.
.
.
.
.
.
1 1 1 1 15
Figure 75. Register 13—3FSK/4FSK Demod Register Map
Rev. B | Page 59 of 64