EVAL-ADF7021DBZ5 Datasheet, PDF (16/64 Pages) Analog Devices – High Performance Narrow-Band Transceiver IC

ADF7021
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Data Sheet
VCOIN 1
CREG1 2
VDD1 3
RFOUT 4
RFGND 5
RFIN 6
RFINB 7
R_LNA 8
VDD4 9
RSET 10
CREG4 11
GND4 12
ADF7021
TOP VIEW
(Not to Scale)
36 CLKOUT
35 TxRxCLK
34 TxRxDATA
33 SWD
32 VDD2
31 CREG2
30 ADCIN
29 GND2
28 SCLK
27 SREAD
26 SDATA
25 SLE
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO GND.
Figure 10. Pin Configuration
Table 8. Pin Function Descriptions
Pin No. Mnemonic
Description
1
VCOIN
The tuning voltage on this pin determines the output frequency of the voltage controlled oscillator (VCO).
The higher the tuning voltage, the higher the output frequency.
2
CREG1
Regulator Voltage for PA Block. Place a series 3.9 Ω resistor and a 100 nF capacitor between this pin and
ground for regulator stability and noise rejection.
3
VDD1
Voltage Supply for PA Block. Place decoupling capacitors of 0.1 μF and 100 pF as close as possible to this pin.
Tie all VDD pins together.
4
RFOUT
The modulated signal is available at this pin. Output power levels are from −16 dBm to +13 dBm. The output
should be impedance matched to the desired load using suitable components (see the Transmitter section).
5
RFGND
Ground for Output Stage of Transmitter. All GND pins should be tied together.
6
RFIN
LNA Input for Receiver Section. Input matching is required between the antenna and the differential LNA
input to ensure maximum power transfer (see the LNA/PA Matching section).
7
RFINB
Complementary LNA Input (see the LNA/PA Matching section).
8
RLNA
External Bias Resistor for LNA. Optimum resistor is 1.1 kΩ with 5% tolerance.
9
VDD4
Voltage Supply for LNA/MIXER Block. This pin should be decoupled to ground with a 10 nF capacitor.
10
RSET
External Resistor. Sets charge pump current and some internal bias currents. Use a 3.6 kΩ resistor with 5% tolerance.
11
CREG4
Regulator Voltage for LNA/MIXER Block. Place a 100 nF capacitor between this pin and GND for regulator
stability and noise rejection.
12, 19, 22 GND4
Ground for LNA/MIXER Block.
13 to 18
MIX_I, MIX_I,
MIX_Q, MIX_Q,
FILT_I, FILT_I
Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left unconnected.
20, 21, 23 FILT_Q, FILT_Q, Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left unconnected.
TEST_A
24
CE
Chip Enable. Bringing CE low puts the ADF7021 into complete power-down. Register values are lost when CE
is low, and the part must be reprogrammed once CE is brought high.
25
SLE
Load Enable, CMOS Input. When SLE goes high, the data stored in the shift registers is loaded into one of the
four latches. A latch is selected using the control bits.
26
SDATA
Serial Data Input. The serial data is loaded MSB first with the 4 LSBs as the control bits. This pin is a high
impedance CMOS input.
27
SREAD
Serial Data Output. This pin is used to feed readback data from the ADF7021 to the microcontroller. The SCLK
input is used to clock each readback bit (for example, AFC or ADC) from the SREAD pin.
28
SCLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into
the 32-bit shift register on the CLK rising edge. This pin is a digital CMOS input.
Rev. B | Page 16 of 64