EVAL-ADF7021DBZ5 Datasheet, PDF (50/64 Pages) Analog Devices – High Performance Narrow-Band Transceiver IC

ADF7021
REGISTER 3—TRANSMIT/RECEIVE CLOCK REGISTER
AGC_CLK_DIVIDE
SEQUENCER_CLK_DIVIDE
CDR_CLK_DIVIDE
DEM_CLK_
DIVIDE
Data Sheet
ADDRESS
BITS
SK8 SK7 ...
0
0
...
0
0
...
.
.
...
1
1
...
1
1
...
SK3 SK2 SK1 SEQ CLK DIVIDE
0011
0102
.
.
.
.
1 1 0 254
1 1 1 255
BK2 BK1 BBOS CLK DIVIDE
004
018
1 0 16
1 1 32
GD6
0
0
...
1
GD5
0
0
...
1
GD4
0
0
...
1
GD3
0
0
...
1
GD2
0
0
...
1
GD1
0
1
...
1
AGC CLK DIVIDE
INVALID
1
...
127
FS8 FS7 ...
0
0
...
0
0
...
.
.
...
1
1
...
1
1
...
OK4 OK3 OK2 OK1
0000
0001
... ... ... ...
1111
DEMOD CLK DIVIDE
INVALID
1
...
15
FS3 FS2 FS1 CDR CLK DIVIDE
0
0
1
1
0
1
0
2
.
.
.
.
1
1
0
254
1
1
1
255
Figure 65. Register 3—Transmit/Receive Clock Register Map
Baseband offset clock frequency (BBOS CLK) must be greater
than 1 MHz and less than 2 MHz, where
BBOS CLK =
XTAL
BBOS _CLK _ DIVIDE
Set the demodulator clock (DEMOD CLK) such that 2 MHz ≤
DEMOD CLK ≤ 15 MHz, where
DEMOD CLK =
XTAL
DEMOD _ CLK _ DIVIDE
For 2FSK/3FSK, the data/clock recovery frequency (CDR CLK)
needs to be within 2% of (32 × data rate). For 4FSK, the CDR
CLK needs to be within 2% of (32 × symbol rate).
DEMOD CLK
CDR CLK =
CDR _ CLK _ DIVIDE
The sequencer clock (SEQ CLK) supplies the clock to the digital
receive block. It should be as close to 100 kHz as possible.
SEQ CLK =
XTAL
SEQ _ CLK _ DIVIDE
The time allowed for each AGC step to settle is determined by
the AGC update rate. It should be set close to 10 kHz.
SEQ CLK
AGC Update Rate [Hz] =
AGC _ CLK _ DIVIDE
Rev. B | Page 50 of 64