EVAL-ADF7021DBZ5 Datasheet, PDF (45/64 Pages) Analog Devices – High Performance Narrow-Band Transceiver IC

Data Sheet
ADF7021
SERIAL INTERFACE
The serial interface allows the user to program the 16-/32-bit
registers using a 3-wire interface (SCLK, SDATA, and SLE).
It consists of a level shifter, 32-bit shift register, and 16 latches.
Signals should be CMOS compatible. The serial interface is
powered by the regulator, and, therefore, is inactive when CE is low.
Data is clocked into the register, MSB first, on the rising edge of
each clock (SCLK). Data is transferred to one of 16 latches on the
rising edge of SLE. The destination latch is determined by the
value of the four control bits (C4 to C1); these are the bottom
4 LSBs, DB3 to DB0, as shown in Figure 2. Data can also be read
back on the SREAD pin.
READBACK FORMAT
The readback operation is initiated by writing a valid control
word to the readback register and enabling the READBACK bit
(R7_DB8 = 1). The readback can begin after the control word
has been latched with the SLE signal. SLE must be kept high
while the data is being read out. Each active edge at the SCLK
pin successively clocks the readback word out at the SREAD
pin, as shown in Figure 57, starting with the MSB first. The data
appearing at the first clock cycle following the latch operation
must be ignored. An extra clock cycle is needed after the 16^th
readback bit to return the SREAD pin to tristate. Therefore, 18
total clock cycles are needed for each read back. After the 18^th
clock cycle, SLE should be brought low.
AFC Readback
The AFC readback is valid only during the reception of FSK
signals with either the linear or correlator demodulator active.
The AFC readback value is formatted as a signed 16-bit integer
comprising Bit RV1 to Bit RV16 and is scaled according to the
following formula:
FREQ RB [Hz] = (AFC_READBACK × DEMOD CLK)/2¹⁸
In the absence of frequency errors, FREQ RB is equal to the IF
frequency of 100 kHz. Note that, for the AFC readback to yield
a valid result, the down converted input signal must not fall outside
the bandwidth of the analog IF filter. At low input signal levels,
the variation in the readback value can be improved by averaging.
RSSI Readback
The format of the readback word is shown in Figure 57. It
comprises the RSSI-level information (Bit RV1 to Bit RV7), the
current filter gain (FG1, FG2), and the current LNA gain (LG1,
LG2) setting. The filter and LNA gain are coded in accordance
with the definitions in the Register 9—AGC Register section. For
signal levels below −100 dBm, averaging the measured RSSI values
improves accuracy. The input power can be calculated from the
RSSI readback value as outlined in the RSSI/AGC section.
Battery Voltage/ADCIN/Temperature Sensor Readback
The battery voltage is measured at Pin VDD4. The readback
information is contained in Bit RV1 to Bit RV7. This also
applies for the readback of the voltage at the ADCIN pin and
the temperature sensor. From the readback information, the
battery or ADCIN voltage can be determined using
VBATTERY = (BATTERY_VOLTAGE_READBACK)/21.1
VADCIN = (ADCIN_VOLTAGE_READBACK)/42.1
The temperature can be calculated using
Temp [°C] = −40 + (68.4 − TEMP_READBACK) × 9.32
Silicon Revision Readback
The silicon revision readback word is valid without setting any
other registers. The silicon revision word is coded with four
quartets in BCD format. The product code (PC) is coded with
three quartets extending from Bit RV5 to Bit RV16. The revision
code (RC) is coded with one quartet extending from Bit RV1 to
Bit RV4. The product code for the ADF7021 should read back
as PC = 0x210. The current revision code should read as RC = 0x4.
Filter Bandwidth Calibration Readback
The filter calibration readback word is contained in Bit RV1 to
Bit RV8. This readback can be used for manual filter adjust, thereby
avoiding the need to do an IF filter calibration in some instances.
The manual adjust value is programmed by R5_DB[14:19]. To
calculate the manual adjust based on a filter calibration readback,
use the following formula:
IF_FILTER_ADJUST = FILTER_CAL_READBACK − 128
The result should be programmed into R5_DB[14:19] as outlined
in the Register 5—IF Filter Setup Register section.
READBACK MODE
READBACK VALUE
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
AFC READBACK
RV16 RV15 RV14 RV13 RV12 RV11 RV10 RV9 RV8 RV7 RV6 RV5 RV4 RV3 RV2 RV1
RSSI READBACK
X
X
X
X
X LG2 LG1 FG2 FG1 RV7 RV6 RV5 RV4 RV3 RV2 RV1
BATTERY VOLTAGE/ADCIN/
TEMP. SENSOR READBACK _X
X
X
X
X
X
X
X
X RV7 RV6 RV5 RV4 RV3 RV2 RV1
SILICON REVISION
RV16 RV15 RV14 RV13 RV12 RV11 RV10 RV9 RV8 RV7 RV6 RV5 RV4 RV3 RV2 RV1
FILTER CAL READBACK
0
0
0
0
0
0
0
0 RV8 RV7 RV6 RV5 RV4 RV3 RV2 RV1
Figure 57. Readback Value Table
Rev. B | Page 45 of 64