EVAL-ADF7021DBZ5 Datasheet, PDF (58/64 Pages) Analog Devices – High Performance Narrow-Band Transceiver IC

ADF7021
REGISTER 11—SYNC WORD DETECT REGISTER
SYNC_BYTE_SEQUENCE
Data Sheet
CONTROL
BITS
SYNC BYTE
PL2 PL1 LENGTH
0 0 12 BITS
0 1 16 BITS
1 0 20 BITS
1 1 24 BITS
Figure 73. Register 11—Sync Word Detect Register Map
MATCHING
MT2 MT1 TOLERANCE
0 0 ACCEPT 0 ERRORS
0 1 ACCEPT 1 ERROR
1 0 ACCEPT 2 ERRORS
1 1 ACCEPT 3 ERRORS
REGISTER 12—SWD/THRESHOLD SETUP REGISTER
DATA_PACKET_LENGTH
CONTROL
BITS
DATA PACKET LENGTH
0 INVALID
1 1 BYTE
... ...
255 255 BYTES
SWD MODE
0 SWD PIN LOW
1 SWD PIN HIGH AFTER NEXT SYNCWORD
2 SWD PIN HIGH AFTER NEXT SYNCWORD
FOR DATA PACKET LENGTH NUMBER OF BYTES
3 INTERRUPT PIN HIGH
LOCK THRESHOLD MODE
0 THRESHOLD FREE RUNNING
1 LOCK THRESHOLD AFTER NEXT SYNCWORD
2 LOCK THRESHOLD AFTER NEXT SYNCWORD
FOR DATA PACKET LENGTH NUMBER OF BYTES
3 LOCK THRESHOLD
Figure 74. Register 12—SWD/Threshold Setup Register Map
Lock threshold locks the threshold of the envelope detector. This has the effect of locking the slicer in linear demodulation and locking
the AFC and AGC loops when using linear or correlator demodulation.
Rev. B | Page 58 of 64