ADSP-SC582 Datasheet, PDF (5/168 Pages) Analog Devices – SHARC plus Dual Core DSP with ARM Cortex-A5

Preliminary Technical Data _{ADSP-SC582/583/584/587/589/ADSP-21583/584/587}
ARM CORTEX-A5 PROCESSOR
The ARM Cortex-A5 processor (Figure 2) is a high performance
processor with the following features:
• Instruction and Data L1 cache units (32/32K bytes)
• In-order pipeline with dynamic branch prediction
• ARM, Thumb, and ThumbEE instruction set support
• TrustZone security extensions
• Harvard level 1 memory system with a memory manage-
ment unit (MMU)
• ARM v7 debug architecture
• Trace support through an embedded trace macrocell
(ETM) interface
• Extension: vector floating-point unit (IEEE754) with trap-
less execution
• Extension: media processing engine (MPE) with NEON
technology
• Extension: Jazelle hardware acceleration
EMBEDDED TRACE MACROCELL
(ETM) INTERFACE
CoreSight INTERFACE
DEBUG
CP15
NEON^TM MEDIA
PROCESSING
ENGINE
CORTEX-A5
PROCESSOR
DATA PROCESSING UNIT (DPU)
DATA MICRO-TLB
PREFETCH UNIT AND BRANCH PREDICTOR (PFU)
INSTRUCTION MICRO-TLB
DATA STORE
BUFFER (STB)
DATA CACHE
UNIT (DCU)
32 KB
MAIN TRANSMISSION
LOOKINSIDE BUFFER (TLB)
INSTRUCTION CACHE
UNIT (ICU)
32 KB
BUS INTERFACE UNIT (BIU)
A5 BUS MASTER PORT
GENERIC INTERRUPT
CONTROLLER
(PrimeCell^® PL-390)
L2 CACHE
CONTROLLER
(CoreLink^TM PL-310)
256 KB
DATA MASTER PORTS
SHARC PROCESSORS
SYSTEM FABRIC
Figure 2. ARM Cortex A-5 Processor Block Diagram
TO OTHER CORES
Rev. PrF | Page 5 of 168 | February 2016