ADSP-SC582 Datasheet, PDF (100/168 Pages) Analog Devices – SHARC plus Dual Core DSP with ARM Cortex-A5

ADSP-SC582/583/584/587/589/ADSP-21583/584/587 ^{Preliminary Technical Data}
Mobile DDR SDRAM Write Cycle Timing
Table 52 and Figure 22 show mobile DDR SDRAM write cycle timing, related to the dynamic memory controller (DMC).
Table 52. Mobile DDR SDRAM Write Cycle Timing, V_{DD_DMCx} Nominal 1.8 V¹
All specifications are based on simulation data and are subject to change without notice.
200 MHz²
Parameter
Min
Max
Switching Characteristics
t_DQSS³
DMCx_DQS Latching Rising Transitions to Associated Clock Edges
0.75
1.25
t_DS
Last Data Valid to DMCx_DQS Delay (Slew > 1 V/ns)
0.48
t_DH
DMCx_DQS to First Data Invalid Delay (Slew > 1 V/ns)
0.48
t_DSS
DMCx_DQS Falling Edge to Clock Setup Time
0.2
t_DSH
DMCx_DQS Falling Edge Hold Time From DMCx_CK
0.2
t_DQSH
DMCx_DQS Input High Pulse Width
0.4
t_DQSL
DMCx_DQS Input Low Pulse Width
0.4
t_WPRE
Write Preamble
0.25
t_WPST
Write Postamble
0.4
t_IPW
Address and Control Output Pulse Width
2.3
t_DIPW
DMCx_DQ and DMCx_DM Output Pulse Width
1.8
1 _{Specifications apply to both DMC0 and DMC1.}
2 _{In order to ensure proper operation of LPDDR, all the LPDDR guidelines must be strictly followed (see Engineer-to-Engineer Note EE-TBD).}
3 _{Write command to first DMCx_DQS delay = WL × tCK + tDQSS.}
Unit
t_CK
ns
ns
t_CK
t_CK
t_CK
t_CK
t_CK
t_CK
ns
ns
DMCx_CK
DMCx_LDQS/DMCx_HDQS
DMCx_DQ0-15/
DMCx_LDQM/DMCx_HDQM
DMCx CONTROL
t_DQSS
t_DSH
t_DSS
Write CMD
t_IPW
t_WPRE
t_DS tDH
t_DIPW
Dn
t_DQSL
t_DQSH
t_WPST
Dn+1
Dn+2
t_DIPW
Dn+3
NOTE: CONTROL = DMCx_CSx, DMCx_CKE, DMCx_RAS, DMCx_CAS, AND DMCx_WE.
ADDRESS = DMCx_A00-13, AND DMCx_BA0-1.
Figure 22. Mobile DDR SDRAM Controller Output AC Timing
Rev. PrF | Page 100 of 168 | February 2016