ADSP-SC582 Datasheet, PDF (140/168 Pages) Analog Devices – SHARC plus Dual Core DSP with ARM Cortex-A5

ADSP-SC582/583/584/587/589/ADSP-21583/584/587 ^{Preliminary Technical Data}
Sony/Philips Digital Interface (S/PDIF) Transmitter
Serial data input to the Sony/Philips Digital Interface (S/PDIF) transmitter can be formatted as left-justified, I²S, or right-justified with
word widths of 16, 18, 20, or 24 bits. The following sections provide timing for the transmitter.
S/PDIF Transmitter-Serial Input Waveforms
Figure 66 shows the right-justified mode. Frame sync is high for the left channel and low for the right channel. Data is valid on the rising
edge of serial clock. The MSB is delayed the minimum in 24-bit output mode or the maximum in 16-bit output mode from a frame sync
transition, so that when there are 64 serial clock periods per frame sync period, the LSB of the data is right-justified to the next frame sync
transition.
Table 89. S/PDIF Transmitter Right-Justified Mode
All specifications are based on simulation data and are subject to change without notice.
Parameter
Nominal
Timing Requirement
t_RJD
Frame Sync to MSB Delay in Right-Justified Mode
16-Bit Word Mode
16
18-Bit Word Mode
14
20-Bit Word Mode
12
24-Bit Word Mode
8
Unit
SCLK
SCLK
SCLK
SCLK
DAI_P20–1
FS
DAI_P20–1
SCLK
DAI_P20–1
SDATA
LSB
LEFT/RIGHT CHANNEL
t_RJD
MSB MSB–1 MSB–2
Figure 66. Right-Justified Mode
LSB+2 LSB+1 LSB
Rev. PrF | Page 140 of 168 | February 2016