ADSP-SC582 Datasheet, PDF (10/168 Pages) Analog Devices – SHARC plus Dual Core DSP with ARM Cortex-A5

ADSP-SC582/583/584/587/589/ADSP-21583/584/587 ^{Preliminary Technical Data}
Core Event Controller (CEC)
The SHARC+ core IVT generates various core interrupts (arith-
metic and circular buffer instruction flow exceptions) and SEC
events (debug/monitor, software). The core only responds to
interrupts which are unmasked (IMASK register).
Instruction Conflict-Cache
The processors include a 32-entry instruction cache that enables
three-bus operation for fetching an instruction and four data
values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses cache. This cache
allows full speed execution of core, looped operations such as
digital filter multiply-accumulates, and FFT butterfly process-
ing. The conflict cache serves for on-chip bus conflicts only.
Branch Target Buffer/Branch Predictor
Implementation of a hardware-based branch predictor (BP) and
branch target buffer (BTB) reduce branch delay. The program
sequencer supports efficient branching using this branch target
buffer (BTB) for conditional and unconditional instructions.
Addressing Spaces
In addition to traditionally supported long-word, normal word,
extended-precision word and short word addressing aliases, the
processors support byte addressing for the data and instruction
accesses. The enhanced ISA/VISA provides new instructions for
accessing all sizes of data from byte space as well as for convert-
ing word addresses to byte and byte to word addresses.
Additional Features
The enhanced ISA/VISA of the ADSP-SC58x/ADSP-2158x pro-
cessors also provides memory barrier instruction (sync) for data
synchronization, exclusive data accesses support for multi-core
data sharing, and exclusive data accesses to enable
multiprocessor programming. To enhance the reliability of
application, L1 data RAMs support parity error detection logic
for every byte. Additionally, the processors detect illegal
opcodes. Core interrupts flag both the errors. Master ports of
the core also detect for failed external accesses.
SYSTEM INFRASTRUCTURE
The following sections describe the system infrastructure of the
ADSP-SC58x/ADSP-2158x processors.
System L2 Memory
A system level L2 memory of 2 Mbits (256 kB) is also available
to both SHARC+ cores, the ARM Cortex-A5 core, and DMA
channels. (See Table 5.) Memory accesses to this memory space
are multi-cycle accesses by both the ARM and SHARC+ cores.
The memory space is used for various cases including:
• ARM-to-SHARC+ core data sharing and inter-core
communications
• Accelerator and peripheral source and destination memory
to avoid having to access data in external memory
• A location for DMA descriptors
• Storage for additional data for either ARM or SHARC+
cores to avoid external memory latencies and reduce exter-
nal memory bandwidth
• Storage for incoming Ethernet traffic to improve
performance
• Storage for data coefficient tables cached by the SHARC+
core
See System Memory Protection Unit (SMPU) for options in
limiting access by specific cores and DMA masters.
The ARM Cortex-A5 core has an L1 instruction and data cache,
each of which is 32 kB in size. An L2 cache controller of 256 kB
is also available. When enabling the caches, accesses to all other
memory spaces (internal and external) go through the cache.
SHARC+ Core L1 Memory in Multiprocessor Space
The ARM Cortex-A5 core can access the L1 memory of the
SHARC+ core. See Table 6 for the L1 memory address in multi-
processor space. The SHARC+ core can access the L1 memory
of the other SHARC+ core in the multiprocessor space.
One-Time-Programmable Memory (OTP)
The processors feature 7K bits of one-time-programmable
(OTP) memory which is memory-map accessible. This memory
stores a unique chip identification and supports secure-boot
and secure operation.
I/O Memory Space
The static memory controller (SMC) is programmed to control
up to two blocks of external memories or memory-mapped
devices, with flexible timing parameters. Each block occupies an
8K byte segment regardless of the size of the device used.
Mapped I/Os also include PCIe data and SPI2 memory address
space. See Table 7.
Rev. PrF | Page 10 of 168 | February 2016