ADSP-SC582 Datasheet, PDF (11/168 Pages) Analog Devices – SHARC plus Dual Core DSP with ARM Cortex-A5

Preliminary Technical Data _{ADSP-SC582/583/584/587/589/ADSP-21583/584/587}
SYSTEM MEMORY MAP
Table 4. L1 Block 0, 1, 2, and 3 SHARC Addressing Memory Map (Private Address Space)
Memory
L1 Block 0 SRAM
(1.5 Mb)
L1 Block 1 SRAM
(1.5 Mb)
L1 Block 2 SRAM
(1 Mb)
L1 Block 3 SRAM
(1 Mb)
Long Word (64 Bits)
0x00048000–
0x0004DFFF
0x00058000–
0x0005DFFF
0x00060000–
0x00063FFF
0x00070000–
0x00073FFF
Extended Precision/
ISA Code
(48 Bits)
0x00090000–
0x00097FFF
0x000B0000–
0x000B7FFF
0x000C0000–
0x000C5554
0x000E0000–
0x000E5554
Normal Word
(32 Bits)
0x00090000–
0x0009BFFF
0x000B0000–
0x000BBFFF
0x000C0000–
0x000C7FFF
0x000E0000–
0x000E7FFF
Short Word/
VISA Code (16 Bits)
0x00120000–
0x00137FFF
0x00160000–
0x00177FFF
0x00180000–
0x0018FFFF
0x001C0000–
0x001CFFFF
Byte Access (8 Bits)
0x00240000–
0x0026FFFF
0x002C0000–
0x002EFFFF
0x00300000–
0x0031FFFF
0x00380000–
0x0039FFFF
Table 5. L2 Memory Addressing Map
Memory
Byte Address Space
ARM – Data Access and
Instruction Fetch
SHARC – Data Access
Normal Word Address
Space for Data Access
SHARC
ARM: 0x00000000–0x00007FFF
L2 Boot-ROM0¹ SHARC/DMA: 0x20000000–0x20007FFF 0x08000000–0x08001FFF
L2 RAM (2 Mb) 0x20080000–0x200BFFFF
0x08020000–0x0802FFFF
Boot ROM1
0x20100000–0x20107FFF
0x08040000–0x08041FFF
L2 ROM1
0x20180000–0x201BFFFF
0x08060000–0x0806FFFF
Boot ROM2
0x20200000–0x20207FFF
0x08080000–0x08081FFF
L2 ROM2
0x20280000–0x202BFFFF
0x080A0000–0x080AFFFF
1 _{From the ARM point of view, L2 Boot-ROM0 byte address space is 0x 0000 0000–0x 0000 7FFF.}
Instruction Fetch
VISA Address Space
SHARC
Instruction Fetch
ISA Address Space
SHARC
0x00B80000–0x00B83FFF 0x00580000–0x00581555
0x00BA0000–0x00BBFFFF 0x005A0000–0x005AAAAF
0x00B00000–0x00B03FFF 0x00500000–0x00501555
0x00B20000–0x00B3FFFF 0x00520000–0x0052AAAF
0x00B40000–0x00B43FFF 0x00540000–0x00541555
0x00B60000–0x00B7FFFF 0x00560000–0x0056AAAF
Table 6. SHARC L1 Memory in Multiprocessor Space
L1 Memory of SHARC1 in
Multiprocessor Space
L1 Memory of SHARC2 in
Multiprocessor Space
Address via Slave1 Port
Address via Slave2 Port
Address via Slave1 Port
Address via Slave2 Port
Memory
Block
Block0
Block1
Block2
Block3
Block0
Block1
Block2
Block3
Block0
Block1
Block2
Block3
Block0
Block1
Block2
Block3
Byte Address Space
for ARM and SHARC
0x28240000–0x28270000
0x282C0000–0x282F0000
0x28300000–0x28320000
0x28380000–0x283A0000
0x28640000–0x28670000
0x286C0000–0x286F0000
0x28700000–0x28720000
0x28780000–0x287A0000
0x28A40000–0x28A70000
0x28AC0000–0x28AF0000
0x28B00000–0x28B20000
0x28B80000–0x28BA0000
0x28E40000–0x28E70000
0x28EC0000–0x28EF0000
0x28F00000–0x28F20000
0x28F80000–0x28FA0000
Normal Word Address Space
for SHARC
0x0A090000–0x0A09C000
0x0A0B0000–0x0A0BC000
0x0A0C0000–0x0A0C8000
0x0A0E0000–0x0A0E8000
0x0A190000–0x0A19C000
0x0A1B0000–0x0A1BC000
0x0A1C0000–0x0A1C8000
0x0A1E0000–0x0A1E8000
0x0A290000–0x0A29C000
0x0A2B0000–0x0A2BC000
0x0A2C0000–0x0A2C8000
0x0A2E0000–0x0A2E8000
0x0A390000–0x0A39C000
0x0A3B0000–0x0A3BC000
0x0A3C0000–0x0A3C8000
0x0A3E0000–0x0A3E8000
Rev. PrF | Page 11 of 168 | February 2016