EVAL-ADM1275EBZ Datasheet, PDF (4/48 Pages) Analog Devices – Hot-Swap Controller and Digital Power

ADM1275
Data Sheet
SPECIFICATIONS
VCC = 2.95 V to 20 V, VCC ≥ VSENSE+, VSENSE+ = 2 V to 20 V, VSENSE = (VSENSE+ − VSENSE−) = 0 V, TA = −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter
Min
POWER SUPPLY
Operating Voltage Range, VCC
2.95
Undervoltage Lockout
2.4
Undervoltage Hysteresis
Quiescent Current, ICC
UV PIN
Input Current, IUV
UV Threshold, UVTH
0.97
UV Threshold Hysteresis, UVHYST
40
UV Glitch Filter, UVGF
2
UV Propagation Delay, UVPD
OV PIN
Input Current, IOV
OV Threshold, OVTH
0.97
OV Threshold Hysteresis, OVHYST
50
OV Glitch Filter, OVGF
0.5
OV Propagation Delay, OVPD
SENSE+ AND SENSE− PINS
Input Current, ISENSEx
Input Imbalance, IΔSENSE
VCAP PIN
Internally Regulated Voltage, VVCAP
2.66
ISET PIN
Reference Select Threshold, VISETRSTH
1.35
Internal Reference, VCLREF
Gain of Current Sense Amplifier, AVCSAMP
Input Current, IISET
GATE PIN
Gate Drive Voltage, ΔVGATE
10
4.5
8
4.5
Gate Pull-Up Current, IGATEUP
−20
Gate Pull-Down Current, IGATEDN_REG
45
Gate Pull-Down Current, IGATEDN_SLOW
5
Gate Pull-Down Current, IGATEDN_FAST
750
Gate Holdoff Resistance
HOT-SWAP SENSE VOLTAGE
Hot-Swap Sense Voltage Current Limit, 19.6
VSENSECL
Foldback Inactive
24.6
19.6
9.6
4.6
Foldback Active
3.5
9.6
Typ Max Unit Test Conditions/Comments
20
V
2.7
V
VCC rising
90
120 mV
5
mA GATE on and power monitor running
100 nA UV ≤ 3.6 V
1.0
1.03 V
UV falling
50
60
mV
7
μs
50 mV overdrive
5
8
μs
UV low to GATE pull-down active
ADM1275-1 and ADM1275-3
100 nA OV ≤ 3.6 V
1.0
1.03 V
OV rising
60
70
mV
1.5
μs
50 mV overdrive
1.0
2
μs
OV high to GATE pull-down active
150 μA Per individual pin; SENSE+, SENSE− = 20 V
5
μA
IΔSENSE = (ISENSE+) − (ISENSE−)
2.7
2.74 V
0 µA ≤ IVCAP ≤ 100 µA; CVCAP = 1 μF
1.5
1.65 V
If VISET > VISETRSTH, an internal 1 V reference (VCLREF) is used
1
V
Accuracies included in total sense voltage accuracies
50
V/V Accuracies included in total sense voltage accuracies
100
nA
VISET ≤ VVCAP
Maximum voltage on the gate is always clamped to ≤31 V
ΔVGATE = VGATE − VSENSE+
12
14
V
15 V ≥ VCC ≥ 8 V; IGATE ≤ 5 μA
13
V
20 V ≥ VCC ≥ 15 V; IGATE ≤ 5 μA
10
V
VSENSE+ = VCC = 5 V; IGATE ≤ 5 μA
6
V
VSENSE+ = VCC = 2.95 V; IGATE ≤ 1 μA
−30
μA
VGATE = 0 V
60
75
μA VGATE ≥ 2 V; VISET = 1.0 V; (SENSE+) − (SENSE−) = 30 mV
10
15
mA VGATE ≥ 2 V
1500 2000 mA VGATE ≥ 12 V; VCC ≥ 12 V
20
Ω
VCC = 0 V
20
20.4
mV VISET > 1.65 V; VFLB > 1.12 V; VGATE = (SENSE+) + 3 V;
IGATE = 0 μA; VSS ≥ 2 V
VGATE = (SENSE+) + 3 V; IGATE = 0 μA; VSS ≥ 2 V
25
25.4
mV VISET = 1.25 V; VFLB > 1.395 V
20
20.4
mV VISET = 1.0 V; VFLB > 1.12 V
10
10.4
mV VISET = 0.5 V; VFLB > 0.57 V
5
5.4
mV VISET = 0.25 V; VFLB > 0.295 V
4
4.5
mV VFLB = 0 V; VGATE = (SENSE+) + 3 V; IGATE = 0 μA; VSS ≥ 1 V
10
10.4
mV VISET > 1.0 V; VFLB = 0.5 V; VGATE = (SENSE+) + 3 V; IGATE = 0 μA;
VSS ≥ 1 V
Rev. D | Page 4 of 48